// ----------------------------------------------------------------------
// This file is automatically generated from the script:
// 
// ./create_headers_from_dos_params_h.pl
// 
// and was applied to the file
// 
// ./dos_param.h
// 
// DO NOT EDIT!!!!!
// ----------------------------------------------------------------------
// 
#ifdef DOS_CBUS_REGISTER_H
#else
#define DOS_CBUS_REGISTER_H


//
// Reading file:  ./dos_param.h
//
//------------------------------------------------------------------------------
// Define all modules' base address under DOS 
// APB allocation from 32'hd0050000
//------------------------------------------------------------------------------
//`define APB_DOS_HCODEC2_ADDR_OFFSET     6'h30 // HCODEC 2
// Define base address for VDEC module under DOS:
//  DOS_VDEC_ASSIST_BASE_ADDR       14'h0000
//  DOS_VDEC_MDEC_BASE_ADDR         14'h0900
//  DOS_VDEC_VLD_BASE_ADDR          14'h0c00
//  DOS_VDEC_IQIDCT_BASE_ADDR       14'h0e00
//  DOS_VDEC_VCPU_BASE_ADDR         14'h0300
//  DOS_VDEC_RESERVED_BASE_ADDR     14'h0f00 // Do not use this offset
// Define base address for DOS top-level register module:
//  DOS_TOP_BASE_ADDR               14'h3f00
//------------------------------------------------------------------------------
// VDEC_ASSIST module level register offset
//------------------------------------------------------------------------------
// -----------------------------------------------
// CBUS_BASE:  DOS_VDEC_ASSIST_CBUS_BASE = 0x00
// -----------------------------------------------
#define VDEC_ASSIST_MMC_CTRL0                      0x0001
#define VDEC_ASSIST_MMC_CTRL1                      0x0002
#define VDEC_ASSIST_AMR1_INT0                      0x0025
#define VDEC_ASSIST_AMR1_INT1                      0x0026
#define VDEC_ASSIST_AMR1_INT2                      0x0027
#define VDEC_ASSIST_AMR1_INT3                      0x0028
#define VDEC_ASSIST_AMR1_INT4                      0x0029
#define VDEC_ASSIST_AMR1_INT5                      0x002a
#define VDEC_ASSIST_AMR1_INT6                      0x002b
#define VDEC_ASSIST_AMR1_INT7                      0x002c
#define VDEC_ASSIST_AMR1_INT8                      0x002d
#define VDEC_ASSIST_AMR1_INT9                      0x002e
#define VDEC_ASSIST_AMR1_INTA                      0x002f
#define VDEC_ASSIST_AMR1_INTB                      0x0030
#define VDEC_ASSIST_AMR1_INTC                      0x0031
#define VDEC_ASSIST_AMR1_INTD                      0x0032
#define VDEC_ASSIST_AMR1_INTE                      0x0033
#define VDEC_ASSIST_AMR1_INTF                      0x0034
#define VDEC_ASSIST_AMR2_INT0                      0x0035
#define VDEC_ASSIST_AMR2_INT1                      0x0036
#define VDEC_ASSIST_AMR2_INT2                      0x0037
#define VDEC_ASSIST_AMR2_INT3                      0x0038
#define VDEC_ASSIST_AMR2_INT4                      0x0039
#define VDEC_ASSIST_AMR2_INT5                      0x003a
#define VDEC_ASSIST_AMR2_INT6                      0x003b
#define VDEC_ASSIST_AMR2_INT7                      0x003c
#define VDEC_ASSIST_AMR2_INT8                      0x003d
#define VDEC_ASSIST_AMR2_INT9                      0x003e
#define VDEC_ASSIST_AMR2_INTA                      0x003f
#define VDEC_ASSIST_AMR2_INTB                      0x0040
#define VDEC_ASSIST_AMR2_INTC                      0x0041
#define VDEC_ASSIST_AMR2_INTD                      0x0042
#define VDEC_ASSIST_AMR2_INTE                      0x0043
#define VDEC_ASSIST_AMR2_INTF                      0x0044
#define VDEC_ASSIST_MBX_SSEL                       0x0045
#define VDEC_ASSIST_TIMER0_LO                      0x0060
#define VDEC_ASSIST_TIMER0_HI                      0x0061
#define VDEC_ASSIST_TIMER1_LO                      0x0062
#define VDEC_ASSIST_TIMER1_HI                      0x0063
#define VDEC_ASSIST_DMA_INT                        0x0064
#define VDEC_ASSIST_DMA_INT_MSK                    0x0065
#define VDEC_ASSIST_DMA_INT2                       0x0066
#define VDEC_ASSIST_DMA_INT_MSK2                   0x0067
#define VDEC_ASSIST_MBOX0_IRQ_REG                  0x0070
#define VDEC_ASSIST_MBOX0_CLR_REG                  0x0071
#define VDEC_ASSIST_MBOX0_MASK                     0x0072
#define VDEC_ASSIST_MBOX0_FIQ_SEL                  0x0073
#define VDEC_ASSIST_MBOX1_IRQ_REG                  0x0074
#define VDEC_ASSIST_MBOX1_CLR_REG                  0x0075
#define VDEC_ASSIST_MBOX1_MASK                     0x0076
#define VDEC_ASSIST_MBOX1_FIQ_SEL                  0x0077
#define VDEC_ASSIST_MBOX2_IRQ_REG                  0x0078
#define VDEC_ASSIST_MBOX2_CLR_REG                  0x0079
#define VDEC_ASSIST_MBOX2_MASK                     0x007a
#define VDEC_ASSIST_MBOX2_FIQ_SEL                  0x007b
//------------------------------------------------------------------------------
// VDEC2_ASSIST module level register offset
//------------------------------------------------------------------------------
// -----------------------------------------------
// CBUS_BASE:  DOS_VDEC2_ASSIST_CBUS_BASE = 0x00
// -----------------------------------------------
#define VDEC2_ASSIST_MMC_CTRL0                     0x0001
#define VDEC2_ASSIST_MMC_CTRL1                     0x0002
#define VDEC2_ASSIST_AMR1_INT0                     0x0025
#define VDEC2_ASSIST_AMR1_INT1                     0x0026
#define VDEC2_ASSIST_AMR1_INT2                     0x0027
#define VDEC2_ASSIST_AMR1_INT3                     0x0028
#define VDEC2_ASSIST_AMR1_INT4                     0x0029
#define VDEC2_ASSIST_AMR1_INT5                     0x002a
#define VDEC2_ASSIST_AMR1_INT6                     0x002b
#define VDEC2_ASSIST_AMR1_INT7                     0x002c
#define VDEC2_ASSIST_AMR1_INT8                     0x002d
#define VDEC2_ASSIST_AMR1_INT9                     0x002e
#define VDEC2_ASSIST_AMR1_INTA                     0x002f
#define VDEC2_ASSIST_AMR1_INTB                     0x0030
#define VDEC2_ASSIST_AMR1_INTC                     0x0031
#define VDEC2_ASSIST_AMR1_INTD                     0x0032
#define VDEC2_ASSIST_AMR1_INTE                     0x0033
#define VDEC2_ASSIST_AMR1_INTF                     0x0034
#define VDEC2_ASSIST_AMR2_INT0                     0x0035
#define VDEC2_ASSIST_AMR2_INT1                     0x0036
#define VDEC2_ASSIST_AMR2_INT2                     0x0037
#define VDEC2_ASSIST_AMR2_INT3                     0x0038
#define VDEC2_ASSIST_AMR2_INT4                     0x0039
#define VDEC2_ASSIST_AMR2_INT5                     0x003a
#define VDEC2_ASSIST_AMR2_INT6                     0x003b
#define VDEC2_ASSIST_AMR2_INT7                     0x003c
#define VDEC2_ASSIST_AMR2_INT8                     0x003d
#define VDEC2_ASSIST_AMR2_INT9                     0x003e
#define VDEC2_ASSIST_AMR2_INTA                     0x003f
#define VDEC2_ASSIST_AMR2_INTB                     0x0040
#define VDEC2_ASSIST_AMR2_INTC                     0x0041
#define VDEC2_ASSIST_AMR2_INTD                     0x0042
#define VDEC2_ASSIST_AMR2_INTE                     0x0043
#define VDEC2_ASSIST_AMR2_INTF                     0x0044
#define VDEC2_ASSIST_MBX_SSEL                      0x0045
#define VDEC2_ASSIST_TIMER0_LO                     0x0060
#define VDEC2_ASSIST_TIMER0_HI                     0x0061
#define VDEC2_ASSIST_TIMER1_LO                     0x0062
#define VDEC2_ASSIST_TIMER1_HI                     0x0063
#define VDEC2_ASSIST_DMA_INT                       0x0064
#define VDEC2_ASSIST_DMA_INT_MSK                   0x0065
#define VDEC2_ASSIST_DMA_INT2                      0x0066
#define VDEC2_ASSIST_DMA_INT_MSK2                  0x0067
#define VDEC2_ASSIST_MBOX0_IRQ_REG                 0x0070
#define VDEC2_ASSIST_MBOX0_CLR_REG                 0x0071
#define VDEC2_ASSIST_MBOX0_MASK                    0x0072
#define VDEC2_ASSIST_MBOX0_FIQ_SEL                 0x0073
#define VDEC2_ASSIST_MBOX1_IRQ_REG                 0x0074
#define VDEC2_ASSIST_MBOX1_CLR_REG                 0x0075
#define VDEC2_ASSIST_MBOX1_MASK                    0x0076
#define VDEC2_ASSIST_MBOX1_FIQ_SEL                 0x0077
#define VDEC2_ASSIST_MBOX2_IRQ_REG                 0x0078
#define VDEC2_ASSIST_MBOX2_CLR_REG                 0x0079
#define VDEC2_ASSIST_MBOX2_MASK                    0x007a
#define VDEC2_ASSIST_MBOX2_FIQ_SEL                 0x007b
//------------------------------------------------------------------------------
// HCODEC_ASSIST module level register offset
//------------------------------------------------------------------------------
// -----------------------------------------------
// CBUS_BASE:  DOS_HCODEC_ASSIST_CBUS_BASE = 0x00
// -----------------------------------------------
#define HCODEC_ASSIST_MMC_CTRL0                    0x0001
#define HCODEC_ASSIST_MMC_CTRL1                    0x0002
#define HCODEC_MFDIN_REG0_CRST                     0x0010
#define HCODEC_MFDIN_REG1_CTRL                     0x0011
#define HCODEC_MFDIN_REG2_STAT                     0x0012
#define HCODEC_MFDIN_REG3_CANV                     0x0013
#define HCODEC_MFDIN_REG4_LNR0                     0x0014
#define HCODEC_MFDIN_REG5_LNR1                     0x0015
#define HCODEC_MFDIN_REG6_DCFG                     0x0016
#define HCODEC_MFDIN_REG7_SCMD                     0x0017
#define HCODEC_MFDIN_REG8_DMBL                     0x0018
#define HCODEC_MFDIN_REG9_ENDN                     0x0019
#define HCODEC_MFDIN_REGA_CAV1                     0x001a
#define HCODEC_MFDIN_REGB_AMPC                     0x001b
#define HCODEC_ASSIST_AMR1_INT0                    0x0025
#define HCODEC_ASSIST_AMR1_INT1                    0x0026
#define HCODEC_ASSIST_AMR1_INT2                    0x0027
#define HCODEC_ASSIST_AMR1_INT3                    0x0028
#define HCODEC_ASSIST_AMR1_INT4                    0x0029
#define HCODEC_ASSIST_AMR1_INT5                    0x002a
#define HCODEC_ASSIST_AMR1_INT6                    0x002b
#define HCODEC_ASSIST_AMR1_INT7                    0x002c
#define HCODEC_ASSIST_AMR1_INT8                    0x002d
#define HCODEC_ASSIST_AMR1_INT9                    0x002e
#define HCODEC_ASSIST_AMR1_INTA                    0x002f
#define HCODEC_ASSIST_AMR1_INTB                    0x0030
#define HCODEC_ASSIST_AMR1_INTC                    0x0031
#define HCODEC_ASSIST_AMR1_INTD                    0x0032
#define HCODEC_ASSIST_AMR1_INTE                    0x0033
#define HCODEC_ASSIST_AMR1_INTF                    0x0034
#define HCODEC_ASSIST_AMR2_INT0                    0x0035
#define HCODEC_ASSIST_AMR2_INT1                    0x0036
#define HCODEC_ASSIST_AMR2_INT2                    0x0037
#define HCODEC_ASSIST_AMR2_INT3                    0x0038
#define HCODEC_ASSIST_AMR2_INT4                    0x0039
#define HCODEC_ASSIST_AMR2_INT5                    0x003a
#define HCODEC_ASSIST_AMR2_INT6                    0x003b
#define HCODEC_ASSIST_AMR2_INT7                    0x003c
#define HCODEC_ASSIST_AMR2_INT8                    0x003d
#define HCODEC_ASSIST_AMR2_INT9                    0x003e
#define HCODEC_ASSIST_AMR2_INTA                    0x003f
#define HCODEC_ASSIST_AMR2_INTB                    0x0040
#define HCODEC_ASSIST_AMR2_INTC                    0x0041
#define HCODEC_ASSIST_AMR2_INTD                    0x0042
#define HCODEC_ASSIST_AMR2_INTE                    0x0043
#define HCODEC_ASSIST_AMR2_INTF                    0x0044
#define HCODEC_ASSIST_MBX_SSEL                     0x0045
#define HCODEC_ASSIST_TIMER0_LO                    0x0060
#define HCODEC_ASSIST_TIMER0_HI                    0x0061
#define HCODEC_ASSIST_TIMER1_LO                    0x0062
#define HCODEC_ASSIST_TIMER1_HI                    0x0063
#define HCODEC_ASSIST_DMA_INT                      0x0064
#define HCODEC_ASSIST_DMA_INT_MSK                  0x0065
#define HCODEC_ASSIST_DMA_INT2                     0x0066
#define HCODEC_ASSIST_DMA_INT_MSK2                 0x0067
#define HCODEC_ASSIST_MBOX0_IRQ_REG                0x0070
#define HCODEC_ASSIST_MBOX0_CLR_REG                0x0071
#define HCODEC_ASSIST_MBOX0_MASK                   0x0072
#define HCODEC_ASSIST_MBOX0_FIQ_SEL                0x0073
#define HCODEC_ASSIST_MBOX1_IRQ_REG                0x0074
#define HCODEC_ASSIST_MBOX1_CLR_REG                0x0075
#define HCODEC_ASSIST_MBOX1_MASK                   0x0076
#define HCODEC_ASSIST_MBOX1_FIQ_SEL                0x0077
#define HCODEC_ASSIST_MBOX2_IRQ_REG                0x0078
#define HCODEC_ASSIST_MBOX2_CLR_REG                0x0079
#define HCODEC_ASSIST_MBOX2_MASK                   0x007a
#define HCODEC_ASSIST_MBOX2_FIQ_SEL                0x007b
//------------------------------------------------------------------------------
// MDEC module level register offset
//------------------------------------------------------------------------------
//
// Reading file:  mdec_regs.h
//
//========================================================================
//  MDEC module level register offset
//========================================================================
// -----------------------------------------------
// CBUS_BASE:  DOS_VDEC_MDEC_CBUS_BASE = 0x09
// -----------------------------------------------
#define MC_CTRL_REG                                0x0900
#define MC_MB_INFO                                 0x0901
#define MC_PIC_INFO                                0x0902
#define MC_HALF_PEL_ONE                            0x0903
#define MC_HALF_PEL_TWO                            0x0904
#define POWER_CTL_MC                               0x0905
#define MC_CMD                                     0x0906
#define MC_CTRL0                                   0x0907
#define MC_PIC_W_H                                 0x0908
#define MC_STATUS0                                 0x0909
#define MC_STATUS1                                 0x090a
#define MC_CTRL1                                   0x090b
#define MC_MIX_RATIO0                              0x090c
#define MC_MIX_RATIO1                              0x090d
#define MC_DP_MB_XY                                0x090e
#define MC_OM_MB_XY                                0x090f
#define PSCALE_RST                                 0x0910
#define PSCALE_CTRL                                0x0911
#define PSCALE_PICI_W                              0x0912
#define PSCALE_PICI_H                              0x0913
#define PSCALE_PICO_W                              0x0914
#define PSCALE_PICO_H                              0x0915
#define PSCALE_PICO_START_X                        0x0916
#define PSCALE_PICO_START_Y                        0x0917
#define PSCALE_DUMMY                               0x0918
#define PSCALE_FILT0_COEF0                         0x0919
#define PSCALE_FILT0_COEF1                         0x091a
#define PSCALE_CMD_CTRL                            0x091b
#define PSCALE_CMD_BLK_X                           0x091c
#define PSCALE_CMD_BLK_Y                           0x091d
#define PSCALE_STATUS                              0x091e
#define PSCALE_BMEM_ADDR                           0x091f
#define PSCALE_BMEM_DAT                            0x0920
#define PSCALE_DRAM_BUF_CTRL                       0x0921
#define PSCALE_MCMD_CTRL                           0x0922
#define PSCALE_MCMD_XSIZE                          0x0923
#define PSCALE_MCMD_YSIZE                          0x0924
#define PSCALE_RBUF_START_BLKX                     0x0925
#define PSCALE_RBUF_START_BLKY                     0x0926
//`define PSCALE_RBUF_MB_WIDTH   8'h27
#define PSCALE_PICO_SHIFT_XY                       0x0928
#define PSCALE_CTRL1                               0x0929
//Bit 15, wmask enable
//Bit 14:13, filt0 srckey_less, 
//Bit 12:11, filt1 srckey_less, in the case of the interpolated data is equal distance to 
//key data and normal data, 00: select normal data, 01: select right data, 10: select key data
//Bit 10:9, srckey mode, 00: equal, 01: less than or equal, 10: great than or equal
//Bit 8, src key enable
//Bit 7:0, y src key
#define PSCALE_SRCKEY_CTRL0                        0x092a
//Bit 15:8, cb src key
//Bit 7:0, cr src key
#define PSCALE_SRCKEY_CTRL1                        0x092b
//Bit 22:16 canvas_rd_addr2
//Bit 14:8 canvas_rd_addr1
//Bit 6:0 canvas_rd_addr1
#define PSCALE_CANVAS_RD_ADDR                      0x092c
//Bit 22:16 canvas_wr_addr2
//Bit 14:8 canvas_wr_addr1
//Bit 6:0 canvas_wr_addr1
#define PSCALE_CANVAS_WR_ADDR                      0x092d
//bit 13:8 pscale thread ID and token 
//bit 7 disable write response count adding to busy bit 
//bit 5:0  pscale prearbitor burst num
#define PSCALE_CTRL2                               0x092e
#define MC_MPORT_CTRL                              0x0940
#define MC_MPORT_DAT                               0x0941
#define MC_WT_PRED_CTRL                            0x0942
#define MC_MBBOT_ST_EVEN_ADDR                      0x0944
#define MC_MBBOT_ST_ODD_ADDR                       0x0945
#define MC_DPDN_MB_XY                              0x0946
#define MC_OMDN_MB_XY                              0x0947
#define MC_HCMDBUF_H                               0x0948
#define MC_HCMDBUF_L                               0x0949
#define MC_HCMD_H                                  0x094a
#define MC_HCMD_L                                  0x094b
#define MC_IDCT_DAT                                0x094c
#define MC_CTRL_GCLK_CTRL                          0x094d
#define MC_OTHER_GCLK_CTRL                         0x094e
//Bit 29:24, mbbot thread ID and token 
//Bit 21:16, mc read/write thread ID and token 
//Bit 13:8,  mbbot pre-arbitor burst number 
//Bit 5:0,   mc pre-arbitor burst number 
#define MC_CTRL2                                   0x094f
// `define DBLK_QUANT            8'h76 // ONLY for $ucode/real/amrisc/rv.s, reg value from apollo
//`define ANC1_CANVAS_ADDR      8'h80
//`define ANC2_CANVAS_ADDR      8'h81
//`define REC_CANVAS_ADDR       8'h89
//`define MDEC_PIC_W          8'h8c
//`define MDEC_PIC_H          8'h8d
#define MDEC_PIC_DC_CTRL                           0x098e
#define MDEC_PIC_DC_STATUS                         0x098f
#define ANC0_CANVAS_ADDR                           0x0990
#define ANC1_CANVAS_ADDR                           0x0991
#define ANC2_CANVAS_ADDR                           0x0992
#define ANC3_CANVAS_ADDR                           0x0993
#define ANC4_CANVAS_ADDR                           0x0994
#define ANC5_CANVAS_ADDR                           0x0995
#define ANC6_CANVAS_ADDR                           0x0996
#define ANC7_CANVAS_ADDR                           0x0997
#define ANC8_CANVAS_ADDR                           0x0998
#define ANC9_CANVAS_ADDR                           0x0999
#define ANC10_CANVAS_ADDR                          0x099a
#define ANC11_CANVAS_ADDR                          0x099b
#define ANC12_CANVAS_ADDR                          0x099c
#define ANC13_CANVAS_ADDR                          0x099d
#define ANC14_CANVAS_ADDR                          0x099e
#define ANC15_CANVAS_ADDR                          0x099f
#define ANC16_CANVAS_ADDR                          0x09a0
#define ANC17_CANVAS_ADDR                          0x09a1
#define ANC18_CANVAS_ADDR                          0x09a2
#define ANC19_CANVAS_ADDR                          0x09a3
#define ANC20_CANVAS_ADDR                          0x09a4
#define ANC21_CANVAS_ADDR                          0x09a5
#define ANC22_CANVAS_ADDR                          0x09a6
#define ANC23_CANVAS_ADDR                          0x09a7
#define ANC24_CANVAS_ADDR                          0x09a8
#define ANC25_CANVAS_ADDR                          0x09a9
#define ANC26_CANVAS_ADDR                          0x09aa
#define ANC27_CANVAS_ADDR                          0x09ab
#define ANC28_CANVAS_ADDR                          0x09ac
#define ANC29_CANVAS_ADDR                          0x09ad
#define ANC30_CANVAS_ADDR                          0x09ae
#define ANC31_CANVAS_ADDR                          0x09af
#define DBKR_CANVAS_ADDR                           0x09b0
#define DBKW_CANVAS_ADDR                           0x09b1
#define REC_CANVAS_ADDR                            0x09b2
//28:24, read/write, current canvas idx, used in h264 only now
//23:0, read only, current canvas address, 23:16, Cr canvas addr, 15:8, Cb canvas addr, 7:0, Y  canvas addr
#define CURR_CANVAS_CTRL                           0x09b3
#define MDEC_PIC_DC_THRESH                         0x09b8
#define MDEC_PICR_BUF_STATUS                       0x09b9
#define MDEC_PICW_BUF_STATUS                       0x09ba
#define MCW_DBLK_WRRSP_CNT                         0x09bb
#define MC_MBBOT_WRRSP_CNT                         0x09bc
#define MDEC_PICW_BUF2_STATUS                      0x09bd
#define WRRSP_FIFO_PICW_DBK                        0x09be
#define WRRSP_FIFO_PICW_MC                         0x09bf
#define AV_SCRATCH_0                               0x09c0
#define AV_SCRATCH_1                               0x09c1
#define AV_SCRATCH_2                               0x09c2
#define AV_SCRATCH_3                               0x09c3
#define AV_SCRATCH_4                               0x09c4
#define AV_SCRATCH_5                               0x09c5
#define AV_SCRATCH_6                               0x09c6
#define AV_SCRATCH_7                               0x09c7
#define AV_SCRATCH_8                               0x09c8
#define AV_SCRATCH_9                               0x09c9
#define AV_SCRATCH_A                               0x09ca
#define AV_SCRATCH_B                               0x09cb
#define AV_SCRATCH_C                               0x09cc
#define AV_SCRATCH_D                               0x09cd
#define AV_SCRATCH_E                               0x09ce
#define AV_SCRATCH_F                               0x09cf
#define AV_SCRATCH_G                               0x09d0
#define AV_SCRATCH_H                               0x09d1
#define AV_SCRATCH_I                               0x09d2
#define AV_SCRATCH_J                               0x09d3
#define AV_SCRATCH_K                               0x09d4
#define AV_SCRATCH_L                               0x09d5
#define AV_SCRATCH_M                               0x09d6
#define AV_SCRATCH_N                               0x09d7
// bit[29:24] A_brst_num_co_mb
// bit[21:16] A_id_co_mb
// bit[11:0] wrrsp_count_co_mb
#define WRRSP_CO_MB                                0x09d8
// bit[29:24] A_brst_num_dcac
// bit[21:16] A_id_dcac
// bit[11:0] wrrsp_count_dcac
#define WRRSP_DCAC                                 0x09d9
//======================================
//  MC Control Register Bits
//
//======================================
// For bits, just copy the defines...don't translate to addresses
    #define MC_ENABLE	    0x0001
    //`define MC_RESET	    16'h0002
    #define SKIP_MB		    0x0004

//======================================
//  MB Info Register Bits
//
//======================================
    #define INTRA_MB	    0x0001

    #define BWD_PRED	    0x0004
    #define FWD_PRED	    0x0008

    #define FLD_MOT		    0x0100
    #define FRM_16x8_MOT	0x0200
    #define DUAL_PRM_MOT	0x0300

    #define FRM_DCT		    0x0000	    // Bit 10
    #define FLD_DCT		    0x0400

//======================================
//  MB Info Register Bits
//
//======================================
    #define I_PIC		    0x0001
    #define P_PIC		    0x0002
    #define B_PIC		    0x0003
    
    #define FLD_PIC		    0x0000	    // Bit 8
    #define FRM_PIC		    0x0100	    
//========================================================================
// DBLK Register:  12'h950 - 12'h97f 
//========================================================================
#define DBLK_RST                                   0x0950
#define DBLK_CTRL                                  0x0951
#define DBLK_MB_WID_HEIGHT                         0x0952
#define DBLK_STATUS                                0x0953
#define DBLK_CMD_CTRL                              0x0954
#define DBLK_MB_XY                                 0x0955
#define DBLK_QP                                    0x0956
#define DBLK_Y_BHFILT                              0x0957
#define DBLK_Y_BHFILT_HIGH                         0x0958
#define DBLK_Y_BVFILT                              0x0959
#define DBLK_CB_BFILT                              0x095a
#define DBLK_CR_BFILT                              0x095b
#define DBLK_Y_HFILT                               0x095c
#define DBLK_Y_HFILT_HIGH                          0x095d
#define DBLK_Y_VFILT                               0x095e
#define DBLK_CB_FILT                               0x095f
#define DBLK_CR_FILT                               0x0960
#define DBLK_BETAX_QP_SEL                          0x0961
#define DBLK_CLIP_CTRL0                            0x0962
#define DBLK_CLIP_CTRL1                            0x0963
#define DBLK_CLIP_CTRL2                            0x0964
#define DBLK_CLIP_CTRL3                            0x0965
#define DBLK_CLIP_CTRL4                            0x0966
#define DBLK_CLIP_CTRL5                            0x0967
#define DBLK_CLIP_CTRL6                            0x0968
#define DBLK_CLIP_CTRL7                            0x0969
#define DBLK_CLIP_CTRL8                            0x096a
#define DBLK_STATUS1                               0x096b
#define DBLK_GCLK_FREE                             0x096c
#define DBLK_GCLK_OFF                              0x096d
#define DBLK_AVSFLAGS                              0x096e
// bit 15:0
#define DBLK_CBPY                                  0x0970
// bit 11:8 -- deblk_cbpy_bottom
// bit 7:4 -- deblk_cbpy_left
// bit 3:0 -- deblk_cbpy_top
#define DBLK_CBPY_ADJ                              0x0971
// bit 7:0 -- deblk_cbpc
#define DBLK_CBPC                                  0x0972
// bit 15 -- bottom_mb
// bit 14 -- left_mb
// bit 13 -- top_mb
// bit 12 -- reserved
// bit 11:8 -- deblk_cbpc_bottom
// bit 7:4 -- deblk_cbpc_left
// bit 3:0 -- deblk_cbpc_top
#define DBLK_CBPC_ADJ                              0x0973
// bit 15:8 -- deblk_hmvd   -- {left_1, left_0, below_1, below_0, block3-0} 
// bit 7:0 -- deblk_vmvd    -- {top_1, top_0, below_1, below_0, block3-0} 
#define DBLK_VHMVD                                 0x0974
// bit 13:12 -- right_vmvd
// bit 11 -- right_above_vmvd
// bit 10 -- left_below_hmvd
// bit 9 -- disable_dblk_luma  
// bit 8 -- disable_dblk_chroma
// bit 7 -- bBelowRefDiff
// bit 6 -- bLeftRefDiff
// bit 5 -- bAboveRefDiff
// bit 4 -- reserved
// bit 3 -- s_below
// bit 2 -- s_left
// bit 1 -- s_above
// bit 0 -- s 
#define DBLK_STRONG                                0x0975
// bit 14:10 -- PQUANT 
// bit 9:5 -- left_PQUANT 
// bit 4:0 -- top_PQUANT 
#define DBLK_RV8_QUANT                             0x0976
#define DBLK_CBUS_HCMD2                            0x0977
#define DBLK_CBUS_HCMD1                            0x0978
#define DBLK_CBUS_HCMD0                            0x0979
#define DBLK_VLD_HCMD2                             0x097a
#define DBLK_VLD_HCMD1                             0x097b
#define DBLK_VLD_HCMD0                             0x097c
#define DBLK_OST_YBASE                             0x097d
#define DBLK_OST_CBCRDIFF                          0x097e
//13:8 dblk thread ID and token 
//5:0  dblk prearbitor burst num
#define DBLK_CTRL1                                 0x097f
// MCRCC_CTL1
// 31:3  <reserved[23:0]>
// 2     <cfg_field_pic>
// 1     <sw_rst>
// 0     <bypass_en>
#define MCRCC_CTL1                                 0x0980
// MCRCC_CTL2
// 31:24    <cfg_cache_anc01_c[7:0]>
// 23:16    <cfg_cache_anc01_y[7:0]>
// 15:8     <cfg_cache_anc00_c[7:0]>
// 7:0      <cfg_cache_anc00_y[7:0]>
#define MCRCC_CTL2                                 0x0981
// MCRCC_CTL3
// 31:24    <cfg_cache_anc11_c[7:0]>
// 23:16    <cfg_cache_anc11_y[7:0]>
// 15:8     <cfg_cache_anc10_c[7:0]>
// 7:0      <cfg_cache_anc10_y[7:0]>
#define MCRCC_CTL3                                 0x0982
// bit[31:10] reserved
// bit[9:0] sw_clock_gating control 
// [9] vdec clk_en for assist and cbus.
// [8] vdec clk_en for ddr
// [7] vdec clk_en for vcpu
// [6] vdec clk_en for assist
// [5] vdec clk_en for dblk
// [4] vdec clk_en for iqidct
// [3] vdec clk_en for mc
// [2] vdec clk_en for pic_dc
// [1] vdec clk_en for psc
// [0] vdec clk_en for vld
#define GCLK_EN                                    0x0983
// [0]  Reserved 
// [1]  Reserved
// [2]  Reset assist, mdec's CBUS
// [3]  Reset mdec's VLD
// [4]  Reset mdec's VLD
// [5]  Reset mdec's VLD
// [6]  Reset mdec's IQIDCT
// [7]  Reset mdec's MC
// [8]  Reset mdec's DBLK
// [9]  Reset mdec's PIC_DC
// [10] Reset mdec's Pscale
// [11] Reset vcpu's MCPU
// [12] Reset vcpu's CCPU
// [13] Reset mmc_pre_arb
#define MDEC_SW_RESET                              0x0984
//DBLK last address 12'h97f
//
// Closing file:  mdec_regs.h
//
//------------------------------------------------------------------------------
// VLD module level register offset
//------------------------------------------------------------------------------
//
// Reading file:  vld_regs.h
//
//========================================================================
//  VLD module level register offset
//========================================================================
// -----------------------------------------------
// CBUS_BASE:  DOS_VDEC_VLD_CBUS_BASE = 0x0c
// -----------------------------------------------
#define VLD_STATUS_CTRL                            0x0c00
//
// bit 10 -- use_old_shift_en
// bit 9 -- output_mv_not_pmv
// bit 8:5 -- force_zigzag
// bit 4 -- force_zigzag_en
// bit 3 -- disable_viff_anempty_int
// bit 2 -- disable_m2_ac_coeff_one_cycle
// bit 1 -- forced_reset  force reset pmv
// bit 0 -- mpeg_type  0:mpeg1 1: mpeg2
#define MPEG1_2_REG                                0x0c01
#define F_CODE_REG                                 0x0c02
#define PIC_HEAD_INFO                              0x0c03
#define SLICE_VER_POS_PIC_TYPE                     0x0c04
#define QP_VALUE_REG                               0x0c05
#define MBA_INC                                    0x0c06
#define MB_MOTION_MODE                             0x0c07
//`define PACKET_BYTE_COUNT   8'h08
// bit 15 -- force_search_startcode_en
// bit 14 -- int_cpu_when_error (before do anything)
// bit 13 -- vld_error_reset
// bit 12 -- return_on_slice_header
// bit 6 -- jpeg_ff00_en 
// bit 5:0 -- vld_power_ctl
#define POWER_CTL_VLD                              0x0c08
#define MB_WIDTH                                   0x0c09
#define SLICE_QP                                   0x0c0a
// `define MB_X_MB_Y           8'h0b   /* current MBX and MBY                  */
#define PRE_START_CODE                             0x0c0b
#define SLICE_START_BYTE_01                        0x0c0c
#define SLICE_START_BYTE_23                        0x0c0d
#define RESYNC_MARKER_LENGTH                       0x0c0e
// bit[6:5] - frame/field info, 01 - top, 10 - bottom, 11 - frame
// bit[4:0] - buffer ID
// L0_BUFF_ID_0, L0_BUFF_ID_1, L1_BUFF_ID_0, L1_BUFF_ID_1
#define DECODER_BUFFER_INFO                        0x0c0f
#define FST_FOR_MV_X                               0x0c10
#define FST_FOR_MV_Y                               0x0c11
#define SCD_FOR_MV_X                               0x0c12
#define SCD_FOR_MV_Y                               0x0c13
#define FST_BAK_MV_X                               0x0c14
#define FST_BAK_MV_Y                               0x0c15
#define SCD_BAK_MV_X                               0x0c16
#define SCD_BAK_MV_Y                               0x0c17
// Bit 7:4 -- read_buffer_interlace  0-progressive, 1-interlace, used in VC1
// bit 3 -- reserved
// bit 2 -- weighting_prediction
// bit 1 -- mb_weighting_flag
// bit 0 -- slice_weighting_flag 
#define VLD_DECODE_CONTROL                         0x0c18
#define VLD_REVERVED_19                            0x0c19
#define VIFF_BIT_CNT                               0x0c1a
#define BYTE_ALIGN_PEAK_HI                         0x0c1b
#define BYTE_ALIGN_PEAK_LO                         0x0c1c
#define NEXT_ALIGN_PEAK                            0x0c1d
// bit 19    : vc1_inv_intra_co_mb_ref_rd
// bit 18    : vc1_inv_co_mb_ref_rd
// bit 17    : vc1_inv_intra_co_mb_ref_wr
// bit 16    : vc1_inv_co_mb_ref_wr
// bit 15    : reserved
// bit 14    : avs_drop_enable
// bit 13:12 : avs_drop_ptr
// bit 11:8  : avs_demu_ctl_reg
// bit 7 : avs_enable
// bit 6 : disable_dblk_hcmd
// bit 5 : disable_mc_hcmd
// bit 4 : first_mode3_set enable
// bit 3 : first_mode3
// bit 2:1 : vc1_profile  0-SP, 1-MP, 2-reserved, 3-AP
// bit 0   : vc1_enable
#define VC1_CONTROL_REG                            0x0c1e
#define PMV1_X                                     0x0c20
#define PMV1_Y                                     0x0c21
#define PMV2_X                                     0x0c22
#define PMV2_Y                                     0x0c23
#define PMV3_X                                     0x0c24
#define PMV3_Y                                     0x0c25
#define PMV4_X                                     0x0c26
#define PMV4_Y                                     0x0c27
// Can't use the same address for different defines
// Therefore, create a single define that covers both
// Only appears to be used in micro-code since the VLD hardware is 
// hard coded.
// `define M4_TABLE_SELECT     8'h28  // Does this exist in HW ? Added from register_mp2.h
// `define M4_TABLE_OUTPUT     8'h28  // Does this exist in HW ? Added from register_mp2.h
#define M4_TABLE_SELECT                            0x0c28
#define M4_CONTROL_REG                             0x0c29
#define BLOCK_NUM                                  0x0c2a
#define PATTERN_CODE                               0x0c2b
#define MB_INFO                                    0x0c2c
#define VLD_DC_PRED                                0x0c2d
#define VLD_ERROR_MASK                             0x0c2e
#define VLD_DC_PRED_C                              0x0c2f
#define LAST_SLICE_MV_ADDR                         0x0c30
#define LAST_MVX                                   0x0c31
#define LAST_MVY                                   0x0c32
#define VLD_C38                                    0x0c38
#define VLD_C39                                    0x0c39
#define VLD_STATUS                                 0x0c3a
#define VLD_SHIFT_STATUS                           0x0c3b
// `define VLD_SHIFT_INFO      8'h3b  // Does this exist in HW ? used in $ucode/mpeg4
#define VOFF_STATUS                                0x0c3c
#define VLD_C3D                                    0x0c3d
#define VLD_DBG_INDEX                              0x0c3e
// vld_buff_info -- (index == 0) 
// Bit[7:6]  mv_UR_ready_cnt;
// Bit[5]  vld_wr_idx
// Bit[4]  iq_rd_idx
// Bit[3]  vld_vi_block_rdy_1
// Bit[2]  vld_vi_block_rdy_2
// Bit[1]  voff_empty_1
// Bit[0]  voff_empty_2
// cabac_buff_info_0 -- (index == 1) 
// Bit[31] shift_data_ready
// Bit[30:29] Reserved
// Bit[28:24] cabac_buffer_ptr
// Bit[23:0] cabac_buffer
// cabac_buff_info_1 -- (index == 2) 
// Bit[31:29] Reserved
// Bit[28:20] Drange
// Bit[19:16] bin_count_4
// Bit[15:13] Reserved
// Bit[12:6] context_mem_do
// Bit[5:3] coeff_state
// Bit[2:0] mvd_state
// h264_mv_present -- (index == 3) 
// Bit[31:16] mv_present_l0
// Bit[15:0] mv_present_l1
// h264_mv_cal_info_0 -- (index == 4) 
// [31:28] mv_cal_state
// [27:24] direct_spatial_cnt
// Bit[23:21] Reserved
// Bit[20] mv_UR_ready_for_mv_cal
// Bit[19] co_mb_mem_ready_for_mv_cal
// Bit[18] mc_dblk_cmd_if_busy
// Bit[17] h264_co_mb_wr_busy
// Bit[16] H264_cbp_blk_ready
// Bit[15] mc_hcmd_rrdy
// Bit[14] mc_hcmd_srdy
// Bit[13] mc_cmd_if_ready
// Bit[12] mc_hcmd_mv_available
// Bit[11:8] mc_cmd_if_state
// Bit[7] dblk_hcmd_rrdy
// Bit[6] dblk_hcmd_srdy
// Bit[5] dblk_cmd_if_ready
// Bit[4] dblk_hcmd_mv_available
// Bit[3:0] dblk_cmd_if_state
// h264_mv_cal_info_1 -- (index == 5) 
//  Bit[31:29] Reserved
//  Bit[28:24] total_mvd_num_l0
//  Bit[23:21] Reserved
//  Bit[20:16] mv_cal_ptr_l0
//  Bit[15:13] Reserved
//  Bit[12:8] mc_hcmd_ptr_l0
//  Bit[7:5] Reserved
//  Bit[4:0] dblk_hcmd_ptr_l0
// h264_mv_cal_info_2 -- (index == 6) 
//  Bit[31:29] Reserved
//  Bit[28:24] total_mvd_num_l1
//  Bit[23:21] Reserved
//  Bit[20:16] mv_cal_ptr_l1
//  Bit[15:13] Reserved
//  Bit[12:8] mc_hcmd_ptr_l1
//  Bit[7:5] Reserved
//  Bit[4:0] dblk_hcmd_ptr_l1
// h264_co_mb_info -- (index == 7)
// Bit[31:26] Reserved
// Bit[25] mv_scale_cal_busy
// Bit[24:20] co_mv_count
// Bit[19:16] co_mv_process_state
// Bit[15] h264_co_mb_rd_busy
// Bit[15] h264_co_mb_rd_ready
// Bit[13:12] co_mv_transfer_block_cnt
// Bit[11:8] co_mv_transfer_ptr
// Bit[7] co_mv_POC_l1_busy
// Bit[6] h264_weight_scale_cal_en
// Bit[5] weight_cal_busy
// Bit[4] weight_cal_not_finished
// Bit[3:0] weight_process_state
#define VLD_DBG_DATA                               0x0c3f
// --------------------------------------------
// VIFIFO DDR Interface
// --------------------------------------------
// The VIFIFO start pointer into DDR memory is a 32-bit number
// The Start pointer will automatically be truncated to land on 
// an 8-byte boundary.  That is, bits [2:0] = 0;
#define VLD_MEM_VIFIFO_START_PTR                   0x0c40
// The current pointer points so some location between the START and END 
// pointers.  The current pointer is a BYTE pointer.  That is, you can 
// point to any BYTE address within the START/END range
#define VLD_MEM_VIFIFO_CURR_PTR                    0x0c41
#define VLD_MEM_VIFIFO_END_PTR                     0x0c42
#define VLD_MEM_VIFIFO_BYTES_AVAIL                 0x0c43
// VIFIFO FIFO Control
// bit  [31:24] viff_empty_int_enable_cpu[7:0] 
// bit  [23:16] viff_empty_int_enable_amrisc[7:0] 
//   -bit 23 Video BUFFER < 0x400 Bytes
//   -bit 22 Video BUFFER < 0x200 Bytes
//   -bit 21 Video BUFFER < 0x100 Bytes
//   -bit 20 Video BUFFER < 0x80 Bytes
//   -bit 19 Video BUFFER < 0x40 Bytes
//   -bit 18 Video BUFFER < 0x20 Bytes
//   -bit 17 vififo  < 16 double words
//   -bit 16 vififo  < 8 double words
// bit  [15:13] unused
// bit  [12]    A_urgent
// bit  [11]    transfer_length 0 - 32x64 Bits per request, 1 - 16x64 Bits per request
// bit  [10]    use_level       Set this bit to 1 to enable filling of the FIFO controlled by the buffer
//                              level control.  If this bit is 0, then use bit[1] to control the enabling of filling
// bit  [9]     Data Ready.     This bit is set when data can be popped
// bit  [8]     fill busy       This bit will be high when we're fetching data from the DDR memory
//                              To reset this module, set cntl_enable = 0, and then wait for busy = 0. 
//                              After that you can pulse cntl_init to start over
// bit  [7]     init_with_cntl_init
// bit  [6]     reserved
// bits [5:3]   endian:         see $lib/rtl/ddr_endian.v
// bit  [2]     cntl_empty_en   Set to 1 to enable reading the DDR memory FIFO
//                              Set cntl_empty_en = cntl_fill_en = 0 when pulsing cntl_init
// bit  [1]     cntl_fill_en    Set to 1 to enable reading data from DDR memory
// bit  [0]     cntl_init:      After setting the read pointers, sizes, channel masks
//                              and read masks, set this bit to 1 and then to 0
//                              NOTE:  You don't need to pulse cntl_init if only the start address is
//                              being changed
#define VLD_MEM_VIFIFO_CONTROL                     0x0c44
// --------------------------------------------
// VIFIFO Buffer Level Manager
// --------------------------------------------
#define VLD_MEM_VIFIFO_WP                          0x0c45
#define VLD_MEM_VIFIFO_RP                          0x0c46
#define VLD_MEM_VIFIFO_LEVEL                       0x0c47
//
// bit  [8]     use_parser_video2_wp
// bit  [7]     vbuf2_out_manual
// bit  [6]     vbuf_out_manual
// bit  [5]     empty (ReadOnly)
// bit  [4]     full (ReadOnly)
// bit  [3:2]   reserved
// bit  [1]     manual mode     Set to 1 for manual write pointer mode
// bit  [0]     Init            Set high then low after everything has been initialized
#define VLD_MEM_VIFIFO_BUF_CNTL                    0x0c48
// bit 31:16 -- drop_bytes
// bit 15:14 -- drop_status (Read-Only)
// bit 13:12 -- sync_match_position (Read-Only)
// bit 11:6 -- reserved
// bit 5:4 -- TIME_STAMP_NUMBER, 0-32bits, 1-64bits, 2-96bits, 3-128bits 
// bit 3 -- stamp_soft_reset
// bit 2 -- TIME_STAMP_length_enable
// bit 1 -- TIME_STAMP_sync64_enable
// bit 0 -- TIME_STAMP_enable
#define VLD_TIME_STAMP_CNTL                        0x0c49
// bit 31:0 -- TIME_STAMP_SYNC_CODE_0
#define VLD_TIME_STAMP_SYNC_0                      0x0c4a
// bit 31:0 -- TIME_STAMP_SYNC_CODE_1 
#define VLD_TIME_STAMP_SYNC_1                      0x0c4b
// bit 31:0 TIME_STAMP_0
#define VLD_TIME_STAMP_0                           0x0c4c
// bit 31:0 TIME_STAMP_1
#define VLD_TIME_STAMP_1                           0x0c4d
// bit 31:0 TIME_STAMP_2
#define VLD_TIME_STAMP_2                           0x0c4e
// bit 31:0 TIME_STAMP_3
#define VLD_TIME_STAMP_3                           0x0c4f
// bit 31:0 TIME_STAMP_LENGTH
#define VLD_TIME_STAMP_LENGTH                      0x0c50
// bit 15:0 vififo_rd_count
#define VLD_MEM_VIFIFO_WRAP_COUNT                  0x0c51
// bit 29:24 A_brst_num
// bit 21:16 A_id
// bit 15:0 level_hold 
#define VLD_MEM_VIFIFO_MEM_CTL                     0x0c52
#define VLD_MEM_VBUF_RD_PTR                        0x0c53
#define VLD_MEM_VBUF2_RD_PTR                       0x0c54
#define VLD_MEM_SWAP_ADDR                          0x0c55
// bit[23:16] - swap_d_count (Read Only)
// bit[15:8]  - swap_a_count (Read Only)
// bit [7] - swap busy (Read Only)
// bit [6:2] - reserved
// bit [1] - 1 - STORE to Memory, 0 - LOAD from Memory
// bit [0] - swap active
#define VLD_MEM_SWAP_CTL                           0x0c56
//
// Closing file:  vld_regs.h
//
//------------------------------------------------------------------------------
// IQ/IDCT module level register offset
//------------------------------------------------------------------------------
//
// Reading file:  iqidct_regs.h
//
//========================================================================
//  IQ/IDCT module level register offset
//========================================================================
// -----------------------------------------------
// CBUS_BASE:  DOS_VDEC_IQIDCT_CBUS_BASE = 0x0e
// -----------------------------------------------
#define VCOP_CTRL_REG                              0x0e00
#define QP_CTRL_REG                                0x0e01
#define INTRA_QUANT_MATRIX                         0x0e02
#define NON_I_QUANT_MATRIX                         0x0e03
#define DC_SCALER                                  0x0e04
#define DC_AC_CTRL                                 0x0e05
// `define RV_AI_CTRL          8'h05  // ONLY for $ucode/real/amrisc/rv.s reg value from apollo
#define DC_AC_SCALE_MUL                            0x0e06
#define DC_AC_SCALE_DIV                            0x0e07
// `define DC_AC_SCALE_RESULT  8'h06
// `define RESERVED_E07        8'h07
#define POWER_CTL_IQIDCT                           0x0e08
#define RV_AI_Y_X                                  0x0e09
#define RV_AI_U_X                                  0x0e0a
#define RV_AI_V_X                                  0x0e0b
// bit 15:0 will count up when rv_ai_mb finished when non zero
// and rv_ai_mb_finished_int will be generate when this is not zero
#define RV_AI_MB_COUNT                             0x0e0c
// For H264 I in PB picture Use -- dma type : h264_next_intra_dma
#define NEXT_INTRA_DMA_ADDRESS                     0x0e0d
// Bit 0 -- constrained_intra_pred_flag for H264
#define IQIDCT_CONTROL                             0x0e0e
// Bit[31:19] Reserved
// Bit[18] iq_waiting
// Bit[17] iq_om_wr_idx
// Bit[16] iq_om_rd_idx
// Bit[15] iq_om_busy
// Bit[14] iq_om_2_busy 
// Bit[13] idx_fifo_0
// Bit[12] idx_fifo_1
// Bit[11] idx_fifo_2
// Bit[10] idx_fifo_3
// Bit[9] idx_fifo_4
// Bit[8] idx_fifo_5
// Bit[7] idx_fifo_6
// Bit[6] idx_fifo_7
// Bit[5:3] idx_fifo_wp
// Bit[2:0] idx_fifo_rp
#define IQIDCT_DEBUG_INFO_0                        0x0e0f
// For RTL Simulation Only
#define DEBLK_CMD                                  0x0e10
// Bit[15+16] ds_mc_valid_2
// Bit[14+16] new_idct1_rd_idx_2
// Bit[13+16] new_idct1_wr_idx_2
// Bit[12+16] idct1_buff0_busy_2
// Bit[11+16] idct1_buff1_busy_2
// Bit[10+16] new_idct1_busy_2
// Bit[9+16] iq_om_8val_2
// Bit[8+16] idct1_pipe_busy_2
// Bit[7+16] wait_mb_left_finish_hold_2
// Bit[6+16] new_idct2_rd_idx_2
// Bit[5+16] new_idct2_wr_idx_2
// Bit[4+16] idct2_buff0_busy_2
// Bit[3+16] idct2_buff1_busy_2
// Bit[2+16] idct2_en_2
// Bit[1+16] new_idct2_busy_2
// Bit[0+16] new_idct1_ready_2
// Bit[15] ds_mc_valid_1
// Bit[14] new_idct1_rd_idx_1
// Bit[13] new_idct1_wr_idx_1
// Bit[12] idct1_buff0_busy_1
// Bit[11] idct1_buff1_busy_1
// Bit[10] new_idct1_busy_1
// Bit[9] iq_om_8val_1
// Bit[8] idct1_pipe_busy_1
// Bit[7] wait_mb_left_finish_hold_1
// Bit[6] new_idct2_rd_idx_1
// Bit[5] new_idct2_wr_idx_1
// Bit[4] idct2_buff0_busy_1
// Bit[3] idct2_buff1_busy_1
// Bit[2] idct2_en_1
// Bit[1] new_idct2_busy_1
// Bit[0] new_idct1_ready_1
#define IQIDCT_DEBUG_IDCT                          0x0e11
// bit 31 -- convas_enable
// bit 30:24 -- convas_x_count ( 8 pixels / 64 bits )
// bit 23:16 -- convas_y_count
// bit 15   -- dcac_dma_busy
// bit 14   -- dcac_dma_urgent
// bit 13:8 -- dcac_dma_count
// bit 7    -- dcac_dma_rw
// bit 6    -- dcac_skip_read_mode
// bit 5:0  -- dcac_dma_offset
#define DCAC_DMA_CTRL                              0x0e12
// when (convas_enable == 0 )
//   bit 31:0 dcac_dma_addr
// when (convas_enable == 1 )
//   bit 31:25 canvas_addr (7 bits)
//   bit 24:12 convas_y_start ( 13 btis )
//   bit 11:0  convas_x_start ( 12 btis )
#define DCAC_DMA_ADDRESS                           0x0e13
// bit 7:0 -- dcac_cpu_addr
#define DCAC_CPU_ADDRESS                           0x0e14
// bit 31:0 -- dcac_cpu_data
#define DCAC_CPU_DATA                              0x0e15
// bit 31:19 -- reserved
// bit 18:16 -- block_num_reg -- Read-Only 
// bit 15:0 -- dcac_mb_count
#define DCAC_MB_COUNT                              0x0e16
// bit 31:18 -- reserved
// For H264 :
//   bit 17:2 -- h264_quant 
//   bit 11:6 -- h264_quant_c 
//   bit  5:0 -- h264_quant_c 
// For VC1 :
//   bit    17 -- qindex_GT_8
//   bit    16 -- HalfQPStep
//   bit 15:12 -- eQuantMode 
//   bit 11:6  -- AltPQuant 
//   bit  5:0  -- PQuant 
//             
#define IQ_QUANT                                   0x0e17
// bit 31:24  -- bitplane_width 
// bit 23:16  -- bitplane_height 
// bit 15:14  -- bitplane_start_x 
// bit 13:12  -- bitplane_start_y 
// bit 11:4   -- reserved
// bit 3:1    -- bitplane_type
// bit 0      -- bitplane_busy
#define VC1_BITPLANE_CTL                           0x0e18
    #define RAM_TEST_CMD        0x002
    #define RAM_TEST_ADDR       0x003
    #define RAM_TEST_DATAH      0x004
    #define RAM_TEST_DATAL      0x005

    #define RAM_TEST_RD_CMD	    0x0000
    #define RAM_TEST_WR_CMD	    0x8000
    #define IDCT_TM2_PT0	    0x0001
    #define IDCT_TM2_PT1	    0x0002
    #define IDCT_TM1_PT0	    0x0004
    #define IDCT_TM1_PT1	    0x0008
    #define IQ_OMEM_PT0	        0x0010
    #define IQ_OMEM_PT1	        0x0020
    #define MC_IMEM_PT0	        0x0040
    #define ALL_RAM_PTS	        0x007f
//======================================
//  VCOP Control Register Bits
//
//======================================
    //`define IQIDCT_RESET	    16'h0001	    // Bit 0
    #define QM_WEN		    0x0002	    // Bit 1
    #define IQIDCT_ENABLE	    0x0004	    // Bit 2
    #define INTRA_QM	    0x0008	    // Bit 3	0 = Use default; 1 = use loaded
    #define NINTRA_QM	    0x0010	    // Bit 4	0 = Use default; 1 = use loaded
//======================================
//  QP Control Register Bits
//
//======================================
    #define INTRA_MODE	    0x0080	    // Bit 7
// Duplicate Address:  When actually used
// please move to a different address
// `define FLD_DCT_TYPE	    16'h0100	    // Bit 8	0 = Frame DCT; 1 = field DCT
//
// Closing file:  iqidct_regs.h
//
//------------------------------------------------------------------------------
// VCPU module level register offset
//------------------------------------------------------------------------------
//
// Reading file:  vcpu_regs.h
//
//========================================================================
//  VCPU module level register offset
//========================================================================
// -----------------------------------------------
// CBUS_BASE:  DOS_VDEC_VCPU_CBUS_BASE = 0x03
// -----------------------------------------------
#define MSP                                        0x0300
#define MPSR                                       0x0301
#define MINT_VEC_BASE                              0x0302
#define MCPU_INTR_GRP                              0x0303
#define MCPU_INTR_MSK                              0x0304
#define MCPU_INTR_REQ                              0x0305
#define MPC_P                                      0x0306
#define MPC_D                                      0x0307
#define MPC_E                                      0x0308
#define MPC_W                                      0x0309
#define MINDEX0_REG                                0x030a
#define MINDEX1_REG                                0x030b
#define MINDEX2_REG                                0x030c
#define MINDEX3_REG                                0x030d
#define MINDEX4_REG                                0x030e
#define MINDEX5_REG                                0x030f
#define MINDEX6_REG                                0x0310
#define MINDEX7_REG                                0x0311
#define MMIN_REG                                   0x0312
#define MMAX_REG                                   0x0313
#define MBREAK0_REG                                0x0314
#define MBREAK1_REG                                0x0315
#define MBREAK2_REG                                0x0316
#define MBREAK3_REG                                0x0317
#define MBREAK_TYPE                                0x0318
#define MBREAK_CTRL                                0x0319
#define MBREAK_STAUTS                              0x031a
#define MDB_ADDR_REG                               0x031b
#define MDB_DATA_REG                               0x031c
#define MDB_CTRL                                   0x031d
#define MSFTINT0                                   0x031e
#define MSFTINT1                                   0x031f
#define CSP                                        0x0320
#define CPSR                                       0x0321
#define CINT_VEC_BASE                              0x0322
#define CCPU_INTR_GRP                              0x0323
#define CCPU_INTR_MSK                              0x0324
#define CCPU_INTR_REQ                              0x0325
#define CPC_P                                      0x0326
#define CPC_D                                      0x0327
#define CPC_E                                      0x0328
#define CPC_W                                      0x0329
#define CINDEX0_REG                                0x032a
#define CINDEX1_REG                                0x032b
#define CINDEX2_REG                                0x032c
#define CINDEX3_REG                                0x032d
#define CINDEX4_REG                                0x032e
#define CINDEX5_REG                                0x032f
#define CINDEX6_REG                                0x0330
#define CINDEX7_REG                                0x0331
#define CMIN_REG                                   0x0332
#define CMAX_REG                                   0x0333
#define CBREAK0_REG                                0x0334
#define CBREAK1_REG                                0x0335
#define CBREAK2_REG                                0x0336
#define CBREAK3_REG                                0x0337
#define CBREAK_TYPE                                0x0338
#define CBREAK_CTRL                                0x0339
#define CBREAK_STAUTS                              0x033a
#define CDB_ADDR_REG                               0x033b
#define CDB_DATA_REG                               0x033c
#define CDB_CTRL                                   0x033d
#define CSFTINT0                                   0x033e
#define CSFTINT1                                   0x033f
#define IMEM_DMA_CTRL                              0x0340
#define IMEM_DMA_ADR                               0x0341
#define IMEM_DMA_COUNT                             0x0342
// bit[29:24] A_brst_num_imem
// bit[21:16] A_id_imem
// bit[11:0] wrrsp_count_imem (reserved)
#define WRRSP_IMEM                                 0x0343
#define LMEM_DMA_CTRL                              0x0350
#define LMEM_DMA_ADR                               0x0351
#define LMEM_DMA_COUNT                             0x0352
// bit[29:24] A_brst_num_lmem
// bit[21:16] A_id_lmem
// bit[11:0] wrrsp_count_lmem 
#define WRRSP_LMEM                                 0x0353
#define MAC_CTRL1                                  0x0360
#define ACC0REG1                                   0x0361
#define ACC1REG1                                   0x0362
#define MAC_CTRL2                                  0x0370
#define ACC0REG2                                   0x0371
#define ACC1REG2                                   0x0372
#define CPU_TRACE                                  0x0380
//
// Closing file:  vcpu_regs.h
//
//------------------------------------------------------------------------------
// HENC module level register offset
//------------------------------------------------------------------------------
//
// Reading file:  henc_regs.h
//
//========================================================================
//  MDEC module level register offset
//========================================================================
// -----------------------------------------------
// CBUS_BASE:  DOS_HCODEC_HENC_CBUS_BASE = 0x0a
// -----------------------------------------------
#define HENC_SCRATCH_0                             0x0ac0
#define HENC_SCRATCH_1                             0x0ac1
#define HENC_SCRATCH_2                             0x0ac2
#define HENC_SCRATCH_3                             0x0ac3
#define HENC_SCRATCH_4                             0x0ac4
#define HENC_SCRATCH_5                             0x0ac5
#define HENC_SCRATCH_6                             0x0ac6
#define HENC_SCRATCH_7                             0x0ac7
#define HENC_SCRATCH_8                             0x0ac8
#define HENC_SCRATCH_9                             0x0ac9
#define HENC_SCRATCH_A                             0x0aca
#define HENC_SCRATCH_B                             0x0acb
#define HENC_SCRATCH_C                             0x0acc
#define HENC_SCRATCH_D                             0x0acd
#define HENC_SCRATCH_E                             0x0ace
#define HENC_SCRATCH_F                             0x0acf
#define HENC_SCRATCH_G                             0x0ad0
#define HENC_SCRATCH_H                             0x0ad1
#define HENC_SCRATCH_I                             0x0ad2
#define HENC_SCRATCH_J                             0x0ad3
#define HENC_SCRATCH_K                             0x0ad4
#define HENC_SCRATCH_L                             0x0ad5
#define HENC_SCRATCH_M                             0x0ad6
#define HENC_SCRATCH_N                             0x0ad7
// bit [7:0] data_feed_buff_id
#define IE_DATA_FEED_BUFF_INFO                     0x0ad8
//
// Closing file:  henc_regs.h
//
//------------------------------------------------------------------------------
// VLC module level register offset
//------------------------------------------------------------------------------
//
// Reading file:  vlc_regs.h
//
//========================================================================
//  VLC module level register offset
//========================================================================
// -----------------------------------------------
// CBUS_BASE:  DOS_HCODEC_VLC_CBUS_BASE = 0x0d
// -----------------------------------------------
// Bit[31:28] - henc_status
// Bit[27:8] - reserved
// Bit[7]    mc_hcmd_buff_enable
// Bit[6]    mc_hcmd_use_mc_hcmd_buff
// Bit[5]    mc_hcmd_use_mc_hcmd_hw_start
// Bit[4]    no_mc_out_null_non_skipped_mb
// Bit[3]    mc_out_even_skipped_mb
// Bit[2] - hcmd_enable
// Bit[1] - vlc_control_enable (0 will treat as soft_reset)
// Bit[0] - vlc_input_enable (enable input interface)
#define VLC_STATUS_CTRL                            0x0d00
// Bit[31:16] - Reserved
// Bit [15]  - enable_free_clk_mc_hcmd_buff
// Bit [14]  - enable_free_clk_reg
// Bit [13]  - enable_free_clk_stream
// Bit [12]  - enable_free_clk_pre_buff
// Bit [11]  - enable_free_clk_vb_buff
// Bit [10]  - enable_free_clk_dc_input
// Bit [9]   - enable_free_clk_input
// Bit [8]   - enable_free_clk_mv_cal
// Bit [7]   - enable_free_clk_status
// Bit [6]   - enable_free_clk_mc_dblk_cmd_if
// Bit [5]   - disable_mvd_enc_finished
// Bit [4]   - I16MB_share_ipred_mode_with_I4MB
// Bit [3]   - fixed_picture_qp
// Bit [2]   - use_set_b8_mode ( not used now)
// Bit [1]   - use_set_mb_skip_run
// Bit [0]   - pop_coeff_even_all_zero
#define VLC_CONFIG                                 0x0d01
// --------------------------------------------
// Bitstream DDR Interface
// --------------------------------------------
#define VLC_VB_START_PTR                           0x0d10
#define VLC_VB_END_PTR                             0x0d11
#define VLC_VB_WR_PTR                              0x0d12
// Read Only, VLC_VB_SW_RD_PTR or VLC_VB_HW_RD_PTR
#define VLC_VB_RD_PTR                              0x0d13
#define VLC_VB_SW_RD_PTR                           0x0d14
// Read Only
#define VLC_VB_LEFT                                0x0d15
// VB FIFO Control
// bit  [31:24] vb_full_int_enable_cpu[7:0] 
// bit  [23:16] vb_full_int_enable_amrisc[7:0] 
//   -bit 23 Video BUFFER LEFT < 0x400 Bytes
//   -bit 22 Video BUFFER LEFT < 0x200 Bytes
//   -bit 21 Video BUFFER LEFT < 0x100 Bytes
//   -bit 20 Video BUFFER LEFT < 0x80 Bytes
//   -bit 19 Video BUFFER LEFT < 0x40 Bytes
//   -bit 18 Video BUFFER LEFT < 0x20 Bytes
//   -bit 17 vbfifo left  < 16 double words (8x64bits)
//   -bit 16 vbfifo left  < 8 double words (4x64bits)
// bit  [15]    wr_ptr_int_enable_cpu
// bit  [14]    wr_ptr_int_enable_amrisc
// bit  [13]    wr_ptr_int (Read Only, write 1 will clear)
// bit  [12]    vb_full_int_enable_cpu(Read Only)
// bit  [11]    vb_full_int_enable_amrisc(Read Only)
// bit  [10]    reserved
// bit  [9]     use_vb_hw_rd_ptr
// bit  [8]     vb_always_ready Set to 1 to ignore vb_level blocking DDR write
// bit  [7]     vb_ready_for_transfer (Read Only)
// bit  [6]     data_ready_for_transfer (Read Only)
// bits [5:3]   vb_endian       Set VB Endian inside DDR memory 
// bit  [2]     vb_write_busy   Read Only - indicate DDR write busy
// bit  [1]     vb_write_en     Set to 1 to enable writing data to DDR memory
// bit  [0]     vb_soft_reset   Soft reset  
#define VLC_VB_CONTROL                             0x0d16
// bit 31    transfer_length 0 - 32x64 Bits per request, 1 - 16x64 Bits per request  // default : 0
// bit 30    A_urgent  // default : 0
// bit 29:24 A_brst_num // default : 0x3f
// bit 23:22 reserved
// bit 21:16 A_id  // default : 0x20 
// bit 15:0  vb_left_hold // default : 0 
#define VLC_VB_MEM_CTL                             0x0d17
// vb_wr_ptr address to generate interrupt
#define VLC_VB_INT_PTR                             0x0d18
// bit[31:12] reserved
// bit[11:0] vlc_wrrsp_count
#define VLC_WRRSP                                  0x0d19
#define VLC_TOTAL_BYTES                            0x0d1a
// bit  [31:26] reserved
// bit  [25]    vb_flush
// bit  [24]    vb_reg_ready  
// bit  [23:16] vb_buff_left     -- Read only
// bit  [15:8]  vb_buff_wr_point -- RW
// bit  [7:0]   vb_buff_rd_point -- RW
#define VLC_VB_BUFF                                0x0d1b
// bit[31]    flush_vlc_pre_buff
// bit[30:27] reserved
// bit[26:24] vb_pre_buff_level
// bit[23:0]  vb_pre_buff_data[55:32] 
#define VLC_VB_PRE_BUFF_HI                         0x0d1c
// bit[31:0] vb_pre_buff_data[31:0]
#define VLC_VB_PRE_BUFF_LOW                        0x0d1d
// bit[31]    stream_encap_enable  // 0x0000(00-03) will be changed to 0x000003(00-03) if enabled
// bit[30:29] stream_encap_delay   // delay bytes for encap used 
// bit[28:24] stream_buff_point
// bit[23:0]  stream_buff_data 
#define VLC_STREAM_BUFF                            0x0d1e
// bit[31]    push_stream_block - Read Only (Will set if vb_buff full)
// bit[30]    push_stream_busy  - Read Only (busy when output one byte from stream_buf (max 2 clocks for 8 bits push)
// bit[29:28] stream_encap_status - Read Only
// bit[27:21] reserved
// Long Mode : (Amrisc need movilo and mvihi high to set stream_info)
//   bit[20:16] push_stream_long_length (0 or 31 : Mid or Short mode)
//   bit[15:0]  push_stream_data
// Mid Mode : (Amrisc need movi to set stream_info) 
//   bit[15:12]] push_stream_mid_length (1-12 : mid mode active, 0-short mode, 15 - byte align)
//   bit[11:0]  push_stream_data
// Short Mode : (Amrisc can use mtspi to push stream directely)
//   bit[7:5] push_stream_short_length (0-5 : short length, else - invalid)
//   bit[4:0]  push_stream_data
#define VLC_PUSH_STREAM                            0x0d1f
// bit[15:8] ELEMENT_LENGTH
// bit[7:1]  reserved
// bit[0]  Write - push start, Read - Push Busy
#define VLC_PUSH_ELEMENT                           0x0d20
#define VLC_ELEMENT_DATA                           0x0d21
// --------------------------------------------
// Picture VLC 
// --------------------------------------------
// (&(int|(~AND_enable))|(|(int&OR_enable)))
// bit[31]    OR interrupt Enable Reserved
// bit[30]    OR interrupt Enable for mv_busy
// bit[29]    OR interrupt Enable for b8_mode_busy
// bit[28]    OR interrupt Enable for mb_skip_run_busy
// bit[27]    OR interrupt Enable for cbp_busy
// bit[26]    OR interrupt Enable for Reserved
// bit[25]    OR interrupt Enable for Reserved
// bit[24]    OR interrupt Enable for mb_info_busy
// bit[23]    AND interrupt Enable Reserved
// bit[22]    AND interrupt Enable for mv_busy
// bit[21]    AND interrupt Enable for b8_mode_busy
// bit[20]    AND interrupt Enable for mb_skip_run_busy
// bit[19]    AND interrupt Enable for cbp_busy 
// bit[18]    AND interrupt Enable for Reserved
// bit[17]    AND interrupt Enable for Reserved        
// bit[16]    AND interrupt Enable for mb_info_busy
// bit[15]    OR interrupt Enable Reserved
// bit[14]    OR interrupt Enable for mvd
// bit[13]    OR interrupt Enable for b8_mode
// bit[12]    OR interrupt Enable for mb_skip_run
// bit[11]    OR interrupt Enable for cbp_ready
// bit[10]    OR interrupt Enable for c_ipred_mode_ready
// bit[9]     OR interrupt Enable for ipred_mode_ready
// bit[8]     OR interrupt Enable for mb_info_ready
// bit[7]     AND interrupt Enable Reserved
// bit[6]     AND interrupt Enable for mvd
// bit[5]     AND interrupt Enable for b8_mode
// bit[4]     AND interrupt Enable for mb_skip_run
// bit[3]     AND interrupt Enable for cbp_ready
// bit[2]     AND interrupt Enable for c_ipred_mode_ready
// bit[1]     AND interrupt Enable for ipred_mode_ready
// bit[0]     AND interrupt Enable for mb_info_ready
#define VLC_INT_CONTROL                            0x0d30
// Bit[31:16] picture_height
// Bit[15:0]  picture_width
#define VLC_PIC_SIZE                               0x0d31
// [31:16] Reserved
// [15:3] pic_width_in_mbs_minus1
// [2:0]  picture_type 
#define VLC_PIC_INFO                               0x0d32
// Bit[31:16] MB_NR
// Bit[15:8] MBY
// Bit[7:0] MBX
#define VLC_PIC_POSITION                           0x0d33
// Bit[31] MV_busy
// Bit[30:6] Reserved
// Bit[15] Reserved
// Bit[14] vlc_input_MV_busy
// Bit[13] vlc_input_b8_mode_busy
// Bit[12] vlc_input_mb_skip_run_busy
// Bit[11] vlc_input_cbp_busy
// Bit[10] Reserved
// Bit[9]  Reserved
// Bit[8] vlc_input_mb_info_busy
// Bit[7] Reserved
// Bit[6] mvd
// Bit[5] b8_mode
// Bit[4] mb_skip_run
// Bit[3] cbp
// Bit[2] c_ipred_mode
// Bit[1] ipred_mode
// Bit[0] mb_info ( mb_type, mb_x, mb_y)
#define VLC_INPUT_STATUS                           0x0d34
// Bit[31:28] detected_mb_type
// Bit[27:16] mb_y 
// Bit[15:4]  mb_x 
// Bit[3:0]   mb_type
#define VLC_MB_INFO                                0x0d35
// commnad 0 -- no pending
// normal command + 1 is pending command
//
// bit 31:28 -- pending command 7
// bit 27:24 -- pending command 6
// bit 23:20 -- pending command 5
// bit 19:16 -- pending command 4
// bit 15:12 -- pending command 3
// bit 11:8  -- pending command 2
// bit  7:4  -- pending command 1
// bit  3:0  -- pending command 0
#define VLC_ENC_PEND_CMD                           0x0d36
// For I Slice
// Bit[31:16] Reserved
// Bit[15:0] IntraType 
#define HENC_TOP_INFO_0                            0x0d37
#define HENC_LEFT_INFO_0                           0x0d38
// For I Slice
// Bit[31:24] V_nnz
// Bit[23:16] U_nnz
// Bit[15:0]  Y_nnz 
#define HENC_TOP_INFO_1                            0x0d39
#define HENC_LEFT_INFO_1                           0x0d3a
// bit[63:0] ipred_mode
#define VLC_IPRED_MODE_HI                          0x0d3b
#define VLC_IPRED_MODE_LO                          0x0d3c
// bit[15:8] SE delta quant 
// bit[7:0]  UE delta quant
#define VLC_DELTA_QP                               0x0d3d
// bit[31:16] Reserved
// bit[15:12] Reserved
// bit[11:8] c_ipred_mode 
// bit[7:0] cbp
#define VLC_MB_HEADER_INFO                         0x0d3e
// bit[31:16] mb_skip_run
// bit[15:0]  b8_mode
#define VLC_P_MB_HEADER_INFO                       0x0d3f
// bit[31]    write_ptr_update
// bit[30]    read_ptr_update
// bit[29:20] coeff_buf_level
// bit[19:10] coeff_buf_write_ptr
// bit[9:0]   coeff_buf_read_ptr
#define VLC_COEFF_BUF_STATUS                       0x0d40
// bit[31:10] Reserved
// bit[9:0] read_req_addr
#define VLC_COEFF_RD_REQ                           0x0d41
// bit[20]   - coeff_buf_read_finished
// bit[19]   - coeff_first
// bit[18:4] - coeff_level 
// bit[3:0]  - coeff_run 
#define VLC_COEFF                                  0x0d42
// bit[31]    - coeff_info_ready
// bit[30:25] - Reserved
// bit[24:15] - block_begin_addr
// bit[14:11] - trailing_one_sign
// bit[10:6]  - total_coeff 
// bit[5:4]   - trailing_ones 
// bit[3:0]   - total_zeros
#define VLC_COEFF_INFO                             0x0d43
// bit[31]    write_ptr_update
// bit[30]    read_ptr_update
// bit[29:25] Reserved
// bit[24:20] dc_buf_level -- 0-16
// bit[19:15] Reserved
// bit[14:10] dc_buf_write_ptr
// bit[9:5]   Reserved
// bit[4:0]   dc_buf_read_ptr
#define VLC_DC_BUF_STATUS                          0x0d44
// bit[31:10] Reserved
// bit[9:4]   Reserved
// bit[3:0]   read_req_addr
#define VLC_DC_RD_REQ                              0x0d45
// bit[31:17] - Reserved
// bit[16]   - dc_first
// bit[15:1] - dc_level 
// bit[0]    - dc_type  0 - CDC, 1 - LDC
#define VLC_DC                                     0x0d46
// bit[31]    - dc_info_ready
// bit[30:25] - Reserved
// bit[24:20] - Reserved
// bit[19:15] - dc_idx_begin_addr
// bit[14:11] - dc_trailing_one_sign
// bit[10:6]  - dc_total_coeff 
// bit[5:4]   - dc_trailing_ones 
// bit[3:0]   - dc_total_zeros
#define VLC_DC_INFO                                0x0d47
// bit[31:4]  - Reserved
// bit[3:0]   - mv_rw_idx  (auto increment when read/write VLC_MV) 
#define VLC_MV_INDEX                               0x0d48
// bit[31:16] - MVY
// bit[15:0]  - MVX
#define VLC_MV                                     0x0d49
// bit[31:16] - MVY
// bitp15:0]  - MVX
// Write to HENC_TOP_MV_0 will cause previous U->UL, UR->U, and UR write
// Read will read U MV only 
#define HENC_TOP_MV_0                              0x0d4a
#define HENC_TOP_MV_1                              0x0d4b
#define HENC_TOP_MV_2                              0x0d4c
#define HENC_TOP_MV_3                              0x0d4d
#define HENC_LEFT_MV_0                             0x0d4e
#define HENC_LEFT_MV_1                             0x0d4f
#define HENC_LEFT_MV_2                             0x0d50
#define HENC_LEFT_MV_3                             0x0d51
// Bit[31:1] Reserved
// Bit[0] top_left_mv_ready
#define TOP_LEFT_READY                             0x0d52
// Bit[31:16] Reserved
// Bit[15:0] mb_skip_run
#define MB_SKIP_RUN                                0x0d53
// Bit[31:16] Reserved
// Bit[15]    Reserved
// Bit[14:13] rd_struct // 00 - frame, 10 - top field, 11 - bottom field
// Bit[12:11] wr_struct // 00 - frame, 10 - top field, 11 - bottom field
// Bit[10:5]  mv_buff_id
// Bit[4:0]   mv_ref
#define VLC_HCMD_CONFIG                            0x0d54
// Bit[9:0] h264_dblk_info
#define VLC_HCMD_DBLK_INFO                         0x0d55
// Bit[3:0] vlc_dbg_idx
#define VLC_DBG_IDX                                0x0d56
// Read Only
#define VLC_DBG_READ                               0x0d57
#define VLC_JPEG_CTRL                              0x0d58
#define VLC_JPEG_COEFF_BUF_STAT                    0x0d59
#define VLC_HUFFMAN_ADDR                           0x0d5a
#define VLC_HUFFMAN_DATA                           0x0d5b
// bit[31:0] enc_mv_bits - including b8_mode and mvd
#define VLC_ENC_MV_BITS                            0x0d5c
// bit[31:0] enc_coeff_bits - including cbp, token, trailing_sign, coeff_enc, h264_totzeros, h264_run
#define VLC_ENC_COEFF_BITS                         0x0d5d
//
// Closing file:  vlc_regs.h
//
//------------------------------------------------------------------------------
// QDCT module level register offset
//------------------------------------------------------------------------------
//
// Reading file:  qdct_regs.h
//
//========================================================================
//  QDCT module level register offset
//========================================================================
// -----------------------------------------------
// CBUS_BASE:  DOS_HCODEC_QDCT_CBUS_BASE = 0x0f
// -----------------------------------------------
// bit[31:28] - mb_info_state
#define QDCT_STATUS_CTRL                           0x0f00
// bit[18]    - enable_free_clk_sad_top
// bit[17]    - enable_free_clk_ie_top
// bit[16]    - enable_free_clk_ie_sub
// bit[15]    - enable_free_clk_mc_out
// bit[14]    - enable_free_clk_i_pred_top
// bit[13]    - enable_free_clk_idct_top
// bit[12]    - enable_free_clk_iq_top
// bit[11]    - enable_free_clk_q_top
// bit[10]    - enable_free_clk_dc_buff_8
// bit[9]     - enable_free_clk_dct_top
// bit[8]     - enable_free_clk_mb_info
// bit[7]     - enable_free_clk_mb_buff
// bit[6]     - enable_free_clk_reg
// bit[5]     - ignore_1_include_2nd_half_c
// bit[4]     - ignore_1_include_2nd_half
// bit[3]     - ignore_t_p8x8
// bit[2]     - not_ignore_dc
// bit[1]     - ignore_small_lac_intra
// bit[0]     - disable_fast_zero_block
#define QDCT_CONFIG                                0x0f01
// bit[31]    - ignore_lac_coeff_en
// bit[30:26] - ignore_lac_coeff_else
// bit[25:21] - ignore_lac_coeff_2 
// bit[20:16] - ignore_lac_coeff_1 
// bit[15]    - ignore_cac_coeff_en
// bit[14:10] - ignore_cac_coeff_else
// bit[9:5]   - ignore_cac_coeff_2 
// bit[4:0]   - ignore_cac_coeff_1 
#define IGNORE_CONFIG                              0x0f02
// bit[31]    - ignore_t_lac_coeff_en
// bit[30:26] - ignore_t_lac_coeff_else
// bit[25:21] - ignore_t_lac_coeff_2 
// bit[20:16] - ignore_t_lac_coeff_1 
// bit[15:0]  - Reserved
#define IGNORE_CONFIG_2                            0x0f03
// --------------------------------------------
// MB DATA DDR Interface
// --------------------------------------------
#define QDCT_MB_START_PTR                          0x0f10
#define QDCT_MB_END_PTR                            0x0f11
#define QDCT_MB_WR_PTR                             0x0f12
#define QDCT_MB_RD_PTR                             0x0f13
#define QDCT_MB_LEVEL                              0x0f14
// bit  [31]    reserved
// bit  [30]    no_wait_after_q_cdc
// bit  [29]    ie_start_int_enable
// bit  [28]    ignore_t_p8x8
// bit  [27]    zero_mc_out_null_non_skipped_mb
// bit  [26]    no_mc_out_null_non_skipped_mb
// bit  [25]    mc_out_even_skipped_mb
// bit  [24]    mc_out_wait_cbp_ready
// bit  [23]    mc_out_wait_mb_type_ready
// bit  [22]    i_pred_int_enable
// bit  [21]    intra_sat8_enable
// bit  [20]    ie_sub_enable
// bit  [19]    i_pred_enable
// bit  [18]    iq_enable
// bit  [17]    idct_enable
// bit  [16]    no_zero_coeff_mb
// bit  [15]    add_zero_coeff_block
// bit  [14]    mb_pause_enable
// bit  [13]    q_enable
// bit  [12]    dct_enable
// bit  [11]    ignore_magic_word
// bit  [10]    mb_info_en
// bit  [9]     mb_info_soft_reset
// bit  [8]     mb_always_ready Set to 1 to ignore mb_level blocking DDR read
// bit  [7]     mb_ready_for_transfer (Read Only)
// bit  [6]     data_ready_for_transfer (Read Only)
// bits [5:3]   mb_endian       Set MB Endian inside DDR memory 
// bit  [2]     mb_read_busy   Read Only - indicate DDR read busy
// bit  [1]     mb_read_en     Set to 1 to enable reading data from DDR memory
// bit  [0]     mb_soft_reset   Soft reset  
#define QDCT_MB_CONTROL                            0x0f15
// bit 31    transfer_length 0 - 32x64 Bits per request, 1 - 16x64 Bits per request  // default : 0
// bit 30    A_urgent  // default : 0
// bit 29:24 A_brst_num // default : 0x3f
// bit 23    reserved
// bit 22    read_till_zero
// bit 21:16 A_id  // default : 0x21 
// bit 15:0  mb_level_hold // default : 0 
#define QDCT_MB_MEM_CTL                            0x0f16
// bit  [31:24] reserved
// bit  [23:16] vb_buff_level     -- Read only
// bit  [15:8]  vb_buff_wr_point -- RW
// bit  [7:0]   vb_buff_rd_point -- RW
#define QDCT_MB_BUFF                               0x0f17
// bit [31:0] mb infor data begin magic word - default : 0xa55aaa55
#define QDCT_MB_MAGIC_WORD                         0x0f18
// Read Only Register
// bit[19]   dct_ready_1
// bit[18]   dct_ready_0
// bit[17]   dct_rd_idx
// bit[16]   dct_wr_idx
// bit[15]   dct_srdy
// bit[14]   dct_rrdy
// bit[13]   Reserved
// bit[12:8] dct_block_number 
// bit[7:4]  dct_rw_addr 
// bit[3:0]  dct_status
#define QDCT_DCT_STATUS                            0x0f19
// bit[3:0]  q_status
#define QDCT_Q_STATUS                              0x0f1a
// bit[31:3] Reserved
// bit[2:0]  picture_type
#define QDCT_PIC_INFO                              0x0f1b
// bit[31:28] Reserved
// bit[27:22] I_pic_quant_c
// bit[21:16] I_pic_quant
// bit[15]    reserved
// bit[14:12] quant_rem_c
// bit[11:8]  quant_per_c
// bit[7]     reserved
// bit[6:4]   quant_rem
// bit[3:0]   quant_per
#define QDCT_Q_QUANT_I                             0x0f1c
// bit[31:28] Reserved
// bit[27:22] P_pic_quant_c
// bit[21:16] P_pic_quant
// bit[15]    reserved
// bit[14:12] quant_rem_c
// bit[11:8]  quant_per_c
// bit[7]     reserved
// bit[6:4]   quant_rem
// bit[3:0]   quant_per
#define QDCT_Q_QUANT_P                             0x0f1d
// bit[31]    mb_info_pause
// bit[30:16] pause_mby
// bit[15:0]  pause_mbx
#define QDCT_MB_PAUSE_CTL                          0x0f1e
// bit[31]   top_control_ready_i_pred
// bit[30:28]top_dma_status   
// bit[27]   top_control_ready_ie
// bit[26:24]Reserved
// bit[23]   ul_mb
// bit[22]   right_mb
// bit[21]   top_mb
// bit[20]   left_mb
// bit[19:8] mb_x
// bit[7:6]  i_pred_ref_idx_L 
// bit[5:4]  i_pred_ref_idx_UL 
// bit[3:2]  i_pred_ref_idx_U
// bit[1:0]  i_pred_ref_idx_UR 
#define QDCT_TOP_CONTROL                           0x0f1f
// bit[31:0] top_base_addr - DDR Memory start address for save top Pixel
#define QDCT_TOP_BASE_MEM                          0x0f20
// bit 15:13 Reserved
// bit 12    A_urgent  // default : 0
// bit 11:6  A_brst_num // default : 0x3f
// bit 5:0   A_id  // default : 0x22
#define QDCT_TOP_MEM_CTL                           0x0f21
// bit [11:0] top_wrrsp_count
#define QDCT_TOP_WRRSP                             0x0f22
// Bit[3:0] qdct_dbg_idx
#define QDCT_DBG_IDX                               0x0f23
// Read Only
#define QDCT_DBG_READ                              0x0f24
#define QDCT_JPEG_CTRL                             0x0f25
#define QDCT_JPEG_X_START_END                      0x0f26
#define QDCT_JPEG_Y_START_END                      0x0f27
#define QDCT_JPEG_QUANT_ADDR                       0x0f28
#define QDCT_JPEG_QUANT_DATA                       0x0f29
#define QDCT_JPEG_SOF_RESUME                       0x0f2a
#define QDCT_JPEG_DCT_STATUS0                      0x0f2b
#define QDCT_JPEG_DCT_STATUS1                      0x0f2c
#define QDCT_JPEG_DCT_COEFF01                      0x0f2d
#define QDCT_JPEG_DCT_COEFF23                      0x0f2e
#define QDCT_JPEG_DCT_COEFF45                      0x0f2f
#define QDCT_JPEG_DCT_COEFF67                      0x0f30
#define QDCT_JPEG_DCT_COEFF89                      0x0f31
// IE/ME share same cbus_base as QDCT
// 
// bit[31]  active_ur_block
// bit[30]  active_ul_block
// bit[9]   ie_c_wait_ie_pause
// bit[8:4] max_ie_result_buff_count 
// bit[3]   ie_wait_for_ie_result  // use for (max_ie_result_buff_count == 0) to wait every block
// bit[2]   reserved
// bit[1]   ie_enable
// bit[0]   ie_soft_reset
#define IE_CONTROL                                 0x0f40
// bit[31:12] Reserved
// bit[11:0]  mb_y
#define IE_MB_POSITION                             0x0f41
// bit[31:16] me_skip_run
// bit[15:8]  reserved
// bit [7:4]  me_b8_mode
// bit [3:0]  ie_me_mb_type
#define IE_ME_MB_INFO                              0x0f42
// bit[3]   ie_result_buff_enable
// bit[2]   ie_result_buff_soft_reset
// bit[1]   sad_enable
// bit[0]   sad_soft_reset
#define SAD_CONTROL                                0x0f43
// bit[31:16] - ie_result_buff_count - read only
// bit[14:12] -current_ie_result (pred_mode) - read only
// bit[11]  top_control_data_buff_wr_ptr - rd/wr 
// bit[10]  top_control_data_buff_rd_ptr - rd/wr 
// bit[9:5] ie_result_buff_wr_ptr        - rd/wr
// bit[4:0] ie_result_buff_rd_ptr        - rd/wr
#define IE_RESULT_BUFFER                           0x0f44
// bit[63:0] ie_i4_pred_mode
#define IE_I4_PRED_MODE_HI                         0x0f45
#define IE_I4_PRED_MODE_LO                         0x0f46
// bit [31:9] reserved
// bit [8:4] i_pred_block_number
// bit [3:0] ie_c_pred_mode
#define IE_C_PRED_MODE                             0x0f47
// 31:16 - Left, 0-select ie_pixel, 1-select mc_data_out
// 15:0  - Top,  0-select ie_pixel, 1-select mc_data_out
#define IE_CUR_REF_SEL                             0x0f48
// bit[31]  enable_f_skip_1_step_3
// bit[30]  enable_f_skip_1_step_2
// bit[29]  enable_f_skip_1_step_1
// bit[28]  step_3_enable
// bit[27]  step_2_sub_pixel
// bit[26]  always_f_skip_step_3 
// bit[25]  always_f_skip_step_2 
// bit[24]  always_f_skip_step_1
// bit[23]  half_pixel_only
// bit[22:11] reserved
// bit[10:9] mv_flexable_ctl 00:0x40, 01:0x80, 10:0xc0, 11 : 0x100
// bit[8]   no_md_ab_rd
// bit[7]   use_dct_state
// bit[6]   enable_free_clk_me_ctl
// bit[5]   enable_free_clk_me_ab
// bit[4]   enable_free_clk_me_cb
// bit[3]   reserved
// bit[2]   me_done_int_enable
// bit[1]   me_enable
// bit[0]   me_soft_reset
#define ME_CONTROL                                 0x0f49
// bit[31:28] Reserved
// bit[27:16] me_start_mby
// bit[15:12] Reserved
// bit[11:0]  me_start_mbx
#define ME_START_POSITION                          0x0f4a
// bit [31:28] me_status - Read only
// bit [27:24] me_cb_status  // current buffer
// bit [23:20] me_ab_status  // anc buffer
// bit [19]    Reserved
// bit [18:16] me_ab_wr_ptr  // read only
// bit [15:4]  me_last_mbx 
// bit [3:1]   me_ab_rd_ptr  // read only
// bit [0]     me_action
#define ME_STATUS                                  0x0f4b
// all Read-only
// bit [31:28] Reserved
// bit [27:16] me_ab_mbx
// bit [15:14] me_cb_wr_ptr
// bit [13:12] me_cb_rd_ptr
// bit [11:0]  me_cb_mbx
#define ME_DEBUG                                   0x0f4c
// bit[29:24] step_3_skip_line 
// bit[23:18] step_2_skip_line 
// bit[17:12] step_1_skip_line 
// bit[11:6]  step_0_skip_line 
// bit[5:0]   read_skip_line 
#define ME_SKIP_LINE                               0x0f4d
// bit 15:13 Reserved
// bit 12    A_urgent  // default : 0
// bit 11:6  A_brst_num // default : 0x3f
// bit 5:0   A_id  // default : 0x23
#define ME_AB_MEM_CTL                              0x0f4e
// bit[31:24] anc_pic_canvas
// bit[23:12] max_me_mby_num
// bit[11:0]  max_me_mbx_num 
#define ME_PIC_INFO                                0x0f4f
// bit [23:12] me_sad_enough_1
// bit [11:0]  me_sad_enough_0
#define ME_SAD_ENOUGH_01                           0x0f50
// bit [23:12] me_sad_enough_3
// bit [11:0]  me_sad_enough_2
#define ME_SAD_ENOUGH_23                           0x0f51
// bit [21:10] me_step0_big_sad
// bit [9:5] me_step0_close_mv_y 
// bit [4:0] me_step0_close_mv_x 
#define ME_STEP0_CLOSE_MV                          0x0f52
// bit[31:24] force_skip_sad_3
// bit[23:16] force_skip_sad_2
// bit[15:08] force_skip_sad_1
// bit[07:00] force_skip_sad_0
#define ME_F_SKIP_SAD                              0x0f53
// bit[31:24] force_skip_weight_3
// bit[23:16] force_skip_weight_2
// bit[15:08] force_skip_weight_1
// bit[07:00] force_skip_weight_0
#define ME_F_SKIP_WEIGHT                           0x0f54
// Merge when (
//              (flex & me_merge_flex_en) | 
//              (big_sad & me_merge_sad_en)|
//              ((~me_merge_flex_en)&(~me_merge_sad_en))
//            ) & 
//            ( small_mv_diff |(~me_merge_small_mv_en))
//            & (me_merge_flex_en | me_merge_sad_en | me_merge_small_mv_en)
// bit[31]   me_merge_mv_en_16
// bit[30]   me_merge_small_mv_en_16
// bit[29]   me_merge_flex_en_16
// bit[28]   me_merge_sad_en_16
// bit[27]   me_merge_mv_en_8
// bit[26]   me_merge_small_mv_en_8
// bit[25]   me_merge_flex_en_8
// bit[24]   me_merge_sad_en_8
// bit[23:18] me_merge_mv_diff_16
// bit[17:12] me_merge_mv_diff_8
// bit[11:0] me_merge_min_sad
#define ME_MV_MERGE_CTL                            0x0f55
// bit[31:24] mv_step_weight_1 
// bit[23:16] mv_pre_weight_1 
// bit [15:0] mv_step_weight_0
// bit[7:0]   mv_pre_weight_0 
#define ME_MV_WEIGHT_01                            0x0f56
// bit[31:24] mv_step_weight_3 
// bit[23:16] mv_pre_weight_3
// bit[15:8]  mv_step_weight_2 
// bit[7:0]   mv_pre_weight_2
#define ME_MV_WEIGHT_23                            0x0f57
// bit[31:24] me_sad_range_inc_3
// bit[23:16] me_sad_range_inc_2
// bit[15:8] me_sad_range_inc_1
// bit[7:0] me_sad_range_inc_0
#define ME_SAD_RANGE_INC                           0x0f58
// bit[31:19]  reserved
// bit[18]     sub_relative_any_1_en
// bit[17]     sub_relative_any_2_en
// bit[16]     sub_relative_any_3_en
// bit[15]     sub_relative_any_4_en
// bit[14]     sub_relative_any_h_en
// bit[13]     sub_make_non_flex_fix
// bit[12]     sub_make_big_non_flex_fix
// bit[11:8]   sub_normal_mv_diff_16
// bit[7:4]    sub_normal_mv_diff_8
// bit[3:2]    Reserved
// bit[1]      sub_merge_enable_16
// bit[0]      sub_merge_enable_8
#define ME_SUB_MERGE_CTL                           0x0f59
// bit[31:28]  sub_ref_mv_diff_near
// bit[27:24]  sub_ref_mv_diff_near_flex
// bit[23:20]  sub_ref_mv_diff
// bit[19:16]  sub_ref_mv_diff_flex
// bit[15:8]   sub_ref_mv_near_weight
// bit[7:0]    sub_ref_mv_weight
#define ME_SUB_REF_MV_CTL                          0x0f5a
// bit[31:24]  sub_weight_max_sad
// bit[23:16]  sub_any_range_sad
// bit[15:8]   sub_any_min_sad
// bit[7:0]    sub_any_max_sad
#define ME_SUB_ANY_WEIGHT_SAD                      0x0f5b
// bit[31:24]  sub_fix_sad
// bit[23:16]  sub_fix_diff_sad
// bit[15:8]   sub_sad_flex_adj
// bit[7:0]    sub_big_non_flex_fix_sad
#define ME_SUB_FIX_SAD                             0x0f5c
// bit[31:24]  sub_fix_min_sad
// bit[23:16]  sub_fix_min_diff_sad
// bit[15:8]   sub_fix_min_sad_2
// bit[7:0]    sub_fix_min_diff_sad_2
#define ME_SUB_FIX_MIN_SAD                         0x0f5d
// bit[31:24]  sub_snap_to_ref_max_sad
// bit[23]     sub_snap_to_ref_non_flex
// bit[22:16]  sub_snap_to_ref_mv_diff
// bit[15:4]   sub_glitch_mv_sad
// bit[3:0]    sub_glitch_mv_diff
#define ME_SUB_SNAP_GLITCH                         0x0f5e
// bit[31:20]  sad_act_limit
// bit[19:8]   s_a_any_sad
// bit[7]      Reserved
// bit[6:5]    sub_merge_method
// bit[4]      use_sub_act_result
// bit[3]      s_a_rnd
// bit[2]      Reserved
// bit[1]      sub_act_en_16
// bit[0]      sub_act_en
#define ME_SUB_ACT_CTL                             0x0f5f
//
// Closing file:  qdct_regs.h
//
//------------------------------------------------------------------------------
// HCODEC MDEC module level register offset
//------------------------------------------------------------------------------
//
// Reading file:  hcodec_mdec_regs.h
//
//========================================================================
//  MDEC module level register offset
//========================================================================
// -----------------------------------------------
// CBUS_BASE:  DOS_HCODEC_HDEC_CBUS_BASE = 0x09
// -----------------------------------------------
//`define HCODEC_MC_CTRL_REG         8'h00
//`define HCODEC_MC_MB_INFO          8'h01
//`define HCODEC_MC_PIC_INFO         8'h02
//`define HCODEC_MC_HALF_PEL_ONE     8'h03
//`define HCODEC_MC_HALF_PEL_TWO     8'h04
//`define HCODEC_POWER_CTL_MC        8'h05
//
//`define HCODEC_MC_CMD			    8'h06
//`define HCODEC_MC_CTRL0			8'h07
//`define HCODEC_MC_PIC_W_H  	    8'h08     
//`define HCODEC_MC_STATUS0		    8'h09
//`define HCODEC_MC_STATUS1		    8'h0a
//`define HCODEC_MC_CTRL1			8'h0b
//`define HCODEC_MC_MIX_RATIO0	    8'h0c
//`define HCODEC_MC_MIX_RATIO1	    8'h0d
//`define HCODEC_MC_DP_MB_XY  	    8'h0e     //read only
//`define HCODEC_MC_OM_MB_XY  	    8'h0f     //read only
//
//`define HCODEC_MC_MPORT_CTRL  	    8'h40    
//`define HCODEC_MC_MPORT_DAT  	    8'h41     
//`define HCODEC_MC_WT_PRED_CTRL  	8'h42     
//`define HCODEC_MC_MBBOT_ST_EVEN_ADDR 8'h44     
//`define HCODEC_MC_MBBOT_ST_ODD_ADDR 8'h45     
//`define HCODEC_MC_DPDN_MB_XY        8'h46    //read only     
//`define HCODEC_MC_OMDN_MB_XY        8'h47    //read only     
//`define HCODEC_MC_HCMDBUF_H        8'h48     
//`define HCODEC_MC_HCMDBUF_L        8'h49     
//`define HCODEC_MC_HCMD_H           8'h4a     //read only     
//`define HCODEC_MC_HCMD_L           8'h4b     //read only     
//`define HCODEC_MC_IDCT_DAT         8'h4c 
//
//`define HCODEC_MC_CTRL_GCLK_CTRL   8'h4d 
//`define HCODEC_MC_OTHER_GCLK_CTRL  8'h4e 
//
////Bit 29:24, mbbot thread ID and token 
////Bit 21:16, mc read/write thread ID and token 
////Bit 13:8,  mbbot pre-arbitor burst number 
////Bit 5:0,   mc pre-arbitor burst number 
//`define HCODEC_MC_CTRL2            8'h4f 
//
//// `define HCODEC_DBLK_QUANT            8'h76 // ONLY for $ucode/real/amrisc/rv.s, reg value from apollo
//
////`define HCODEC_ANC1_CANVAS_ADDR      8'h80
////`define HCODEC_ANC2_CANVAS_ADDR      8'h81
//
////`define HCODEC_REC_CANVAS_ADDR       8'h89
//
////`define HCODEC_MDEC_PIC_W          8'h8c
////`define HCODEC_MDEC_PIC_H          8'h8d
//`define HCODEC_MDEC_PIC_DC_CTRL    8'h8e
//`define HCODEC_MDEC_PIC_DC_STATUS  8'h8f
//
//`define HCODEC_ANC0_CANVAS_ADDR      8'h90
//`define HCODEC_ANC1_CANVAS_ADDR      8'h91
//`define HCODEC_ANC2_CANVAS_ADDR      8'h92
//`define HCODEC_ANC3_CANVAS_ADDR      8'h93
//`define HCODEC_ANC4_CANVAS_ADDR      8'h94
//`define HCODEC_ANC5_CANVAS_ADDR      8'h95
//`define HCODEC_ANC6_CANVAS_ADDR      8'h96
//`define HCODEC_ANC7_CANVAS_ADDR      8'h97
//`define HCODEC_ANC8_CANVAS_ADDR      8'h98
//`define HCODEC_ANC9_CANVAS_ADDR      8'h99
//`define HCODEC_ANC10_CANVAS_ADDR     8'h9a
//`define HCODEC_ANC11_CANVAS_ADDR     8'h9b
//`define HCODEC_ANC12_CANVAS_ADDR     8'h9c
//`define HCODEC_ANC13_CANVAS_ADDR     8'h9d
//`define HCODEC_ANC14_CANVAS_ADDR     8'h9e
//`define HCODEC_ANC15_CANVAS_ADDR     8'h9f
//`define HCODEC_ANC16_CANVAS_ADDR     8'ha0
//`define HCODEC_ANC17_CANVAS_ADDR     8'ha1
//`define HCODEC_ANC18_CANVAS_ADDR     8'ha2
//`define HCODEC_ANC19_CANVAS_ADDR     8'ha3
//`define HCODEC_ANC20_CANVAS_ADDR     8'ha4
//`define HCODEC_ANC21_CANVAS_ADDR     8'ha5
//`define HCODEC_ANC22_CANVAS_ADDR     8'ha6
//`define HCODEC_ANC23_CANVAS_ADDR     8'ha7
//`define HCODEC_ANC24_CANVAS_ADDR     8'ha8
//`define HCODEC_ANC25_CANVAS_ADDR     8'ha9
//`define HCODEC_ANC26_CANVAS_ADDR     8'haa
//`define HCODEC_ANC27_CANVAS_ADDR     8'hab
//`define HCODEC_ANC28_CANVAS_ADDR     8'hac
//`define HCODEC_ANC29_CANVAS_ADDR     8'had
//`define HCODEC_ANC30_CANVAS_ADDR     8'hae
//`define HCODEC_ANC31_CANVAS_ADDR     8'haf
//
//`define HCODEC_DBKR_CANVAS_ADDR      8'hb0
//`define HCODEC_DBKW_CANVAS_ADDR      8'hb1
//`define HCODEC_REC_CANVAS_ADDR       8'hb2
//
////28:24, read/write, current canvas idx, used in h264 only now
////23:0, read only, current canvas address, 23:16, Cr canvas addr, 15:8, Cb canvas addr, 7:0, Y  canvas addr
//`define HCODEC_CURR_CANVAS_CTRL      8'hb3
//
//`define HCODEC_MDEC_PIC_DC_THRESH    8'hb8
//`define HCODEC_MDEC_PICR_BUF_STATUS  8'hb9
//`define HCODEC_MDEC_PICW_BUF_STATUS  8'hba
//`define HCODEC_MCW_DBLK_WRRSP_CNT    8'hbb
//
//`define HCODEC_AV_SCRATCH_0          8'hc0
//`define HCODEC_AV_SCRATCH_1          8'hc1
//`define HCODEC_AV_SCRATCH_2          8'hc2
//`define HCODEC_AV_SCRATCH_3          8'hc3
//`define HCODEC_AV_SCRATCH_4          8'hc4
//`define HCODEC_AV_SCRATCH_5          8'hc5
//`define HCODEC_AV_SCRATCH_6          8'hc6
//`define HCODEC_AV_SCRATCH_7          8'hc7
//`define HCODEC_AV_SCRATCH_8          8'hc8
//`define HCODEC_AV_SCRATCH_9          8'hc9
//`define HCODEC_AV_SCRATCH_A          8'hca
//`define HCODEC_AV_SCRATCH_B          8'hcb
//`define HCODEC_AV_SCRATCH_C          8'hcc
//`define HCODEC_AV_SCRATCH_D          8'hcd
//`define HCODEC_AV_SCRATCH_E          8'hce
//`define HCODEC_AV_SCRATCH_F          8'hcf
//`define HCODEC_AV_SCRATCH_G          8'hd0
//`define HCODEC_AV_SCRATCH_H          8'hd1
//`define HCODEC_AV_SCRATCH_I          8'hd2
//`define HCODEC_AV_SCRATCH_J          8'hd3
//`define HCODEC_AV_SCRATCH_K          8'hd4
//`define HCODEC_AV_SCRATCH_L          8'hd5
//`define HCODEC_AV_SCRATCH_M          8'hd6
//`define HCODEC_AV_SCRATCH_N          8'hd7
//
//// bit[29:24] A_brst_num_co_mb
//// bit[21:16] A_id_co_mb
//// bit[11:0] wrrsp_count_co_mb
//`define HCODEC_WRRSP_CO_MB           8'hd8 
//// bit[29:24] A_brst_num_dcac
//// bit[21:16] A_id_dcac
//// bit[11:0] wrrsp_count_dcac
//`define HCODEC_WRRSP_DCAC            8'hd9 
//
////======================================
////  MC Control Register Bits
////
////======================================
//// For bits, just copy the defines...don't translate to addresses
//    `define HCODEC_MC_ENABLE	    16'h0001
//    //`define MC_RESET	    16'h0002
//    `define HCODEC_SKIP_MB		    16'h0004
//
////======================================
////  MB Info Register Bits
////
////======================================
//    `define HCODEC_INTRA_MB	    16'h0001
//
//    `define HCODEC_BWD_PRED	    16'h0004
//    `define HCODEC_FWD_PRED	    16'h0008
//
//    `define HCODEC_FLD_MOT		    16'h0100
//    `define HCODEC_FRM_16x8_MOT	16'h0200
//    `define HCODEC_DUAL_PRM_MOT	16'h0300
//
//    `define HCODEC_FRM_DCT		    16'h0000	    // Bit 10
//    `define HCODEC_FLD_DCT		    16'h0400
//
////======================================
////  MB Info Register Bits
////
////======================================
//    `define HCODEC_I_PIC		    16'h0001
//    `define HCODEC_P_PIC		    16'h0002
//    `define HCODEC_B_PIC		    16'h0003
//    
//    `define HCODEC_FLD_PIC		    16'h0000	    // Bit 8
//    `define HCODEC_FRM_PIC		    16'h0100	    
//
////========================================================================
//// DBLK Register:  12'h950 - 12'h97f 
////========================================================================
//`define HCODEC_DBLK_RST                8'h50
//`define HCODEC_DBLK_CTRL               8'h51
//`define HCODEC_DBLK_MB_WID_HEIGHT      8'h52
//`define HCODEC_DBLK_STATUS             8'h53
//`define HCODEC_DBLK_CMD_CTRL           8'h54
//`define HCODEC_DBLK_MB_XY              8'h55
//`define HCODEC_DBLK_QP                 8'h56
//`define HCODEC_DBLK_Y_BHFILT           8'h57
//`define HCODEC_DBLK_Y_BHFILT_HIGH      8'h58
//`define HCODEC_DBLK_Y_BVFILT           8'h59
//`define HCODEC_DBLK_CB_BFILT           8'h5a
//`define HCODEC_DBLK_CR_BFILT           8'h5b
//`define HCODEC_DBLK_Y_HFILT            8'h5c
//`define HCODEC_DBLK_Y_HFILT_HIGH       8'h5d
//`define HCODEC_DBLK_Y_VFILT            8'h5e
//`define HCODEC_DBLK_CB_FILT            8'h5f
//`define HCODEC_DBLK_CR_FILT            8'h60
//`define HCODEC_DBLK_BETAX_QP_SEL       8'h61
//`define HCODEC_DBLK_CLIP_CTRL0         8'h62
//`define HCODEC_DBLK_CLIP_CTRL1         8'h63
//`define HCODEC_DBLK_CLIP_CTRL2         8'h64
//`define HCODEC_DBLK_CLIP_CTRL3         8'h65
//`define HCODEC_DBLK_CLIP_CTRL4         8'h66
//`define HCODEC_DBLK_CLIP_CTRL5         8'h67
//`define HCODEC_DBLK_CLIP_CTRL6         8'h68
//`define HCODEC_DBLK_CLIP_CTRL7         8'h69
//`define HCODEC_DBLK_CLIP_CTRL8         8'h6a
//
//`define HCODEC_DBLK_STATUS1            8'h6b
//`define HCODEC_DBLK_GCLK_FREE          8'h6c
//`define HCODEC_DBLK_GCLK_OFF           8'h6d
//
//`define HCODEC_DBLK_AVSFLAGS           8'h6e
//
//// bit 15:0
//`define HCODEC_DBLK_CBPY               8'h70
//// bit 11:8 -- deblk_cbpy_bottom
//// bit 7:4 -- deblk_cbpy_left
//// bit 3:0 -- deblk_cbpy_top
//`define HCODEC_DBLK_CBPY_ADJ           8'h71
//// bit 7:0 -- deblk_cbpc
//`define HCODEC_DBLK_CBPC               8'h72
//// bit 15 -- bottom_mb
//// bit 14 -- left_mb
//// bit 13 -- top_mb
//// bit 12 -- reserved
//// bit 11:8 -- deblk_cbpc_bottom
//// bit 7:4 -- deblk_cbpc_left
//// bit 3:0 -- deblk_cbpc_top
//`define HCODEC_DBLK_CBPC_ADJ           8'h73
//// bit 15:8 -- deblk_hmvd   -- {left_1, left_0, below_1, below_0, block3-0} 
//// bit 7:0 -- deblk_vmvd    -- {top_1, top_0, below_1, below_0, block3-0} 
//`define HCODEC_DBLK_VHMVD              8'h74
//// bit 13:12 -- right_vmvd
//// bit 11 -- right_above_vmvd
//// bit 10 -- left_below_hmvd
//// bit 9 -- disable_dblk_luma  
//// bit 8 -- disable_dblk_chroma
//// bit 7 -- bBelowRefDiff
//// bit 6 -- bLeftRefDiff
//// bit 5 -- bAboveRefDiff
//// bit 4 -- reserved
//// bit 3 -- s_below
//// bit 2 -- s_left
//// bit 1 -- s_above
//// bit 0 -- s 
//`define HCODEC_DBLK_STRONG             8'h75
//// bit 14:10 -- PQUANT 
//// bit 9:5 -- left_PQUANT 
//// bit 4:0 -- top_PQUANT 
//`define HCODEC_DBLK_RV8_QUANT          8'h76
//
//`define HCODEC_DBLK_CBUS_HCMD2         8'h77
//`define HCODEC_DBLK_CBUS_HCMD1         8'h78
//`define HCODEC_DBLK_CBUS_HCMD0         8'h79
//`define HCODEC_DBLK_VLD_HCMD2          8'h7a
//`define HCODEC_DBLK_VLD_HCMD1          8'h7b
//`define HCODEC_DBLK_VLD_HCMD0          8'h7c
//
//`define HCODEC_DBLK_OST_YBASE          8'h7d
//`define HCODEC_DBLK_OST_CBCRDIFF       8'h7e
//
////13:8 dblk thread ID and token 
////5:0  dblk prearbitor burst num
//`define HCODEC_DBLK_CTRL1              8'h7f
//
////DBLK last address 12'h97f
//
// Closing file:  hcodec_mdec_regs.h
//
//------------------------------------------------------------------------------
// HCODEC VLD module level register offset
//------------------------------------------------------------------------------
//
// Reading file:  hcodec_vld_regs.h
//
//========================================================================
//  VLD module level register offset
//========================================================================
// -----------------------------------------------
// CBUS_BASE:  DOS_HCODEC_VLD_CBUS_BASE = 0x0c
// -----------------------------------------------
//
//`define HCODEC_VLD_STATUS_CTRL     8'h00
////
//// bit 10 -- use_old_shift_en
//// bit 9 -- output_mv_not_pmv
//// bit 8:5 -- force_zigzag
//// bit 4 -- force_zigzag_en
//// bit 3 -- disable_viff_anempty_int
//// bit 2 -- disable_m2_ac_coeff_one_cycle
//// bit 1 -- forced_reset  force reset pmv
//// bit 0 -- mpeg_type  0:mpeg1 1: mpeg2
//`define HCODEC_MPEG1_2_REG         8'h01
//`define HCODEC_F_CODE_REG          8'h02
//`define HCODEC_PIC_HEAD_INFO       8'h03
//`define HCODEC_SLICE_VER_POS_PIC_TYPE  8'h04
//`define HCODEC_QP_VALUE_REG        8'h05
//`define HCODEC_MBA_INC             8'h06
//`define HCODEC_MB_MOTION_MODE      8'h07
////`define HCODEC_PACKET_BYTE_COUNT   8'h08
//// bit 15 -- force_search_startcode_en
//// bit 14 -- int_cpu_when_error (before do anything)
//// bit 13 -- vld_error_reset
//// bit 12 -- return_on_slice_header
//// bit 6 -- jpeg_ff00_en 
//// bit 5:0 -- vld_power_ctl
//`define HCODEC_POWER_CTL_VLD       8'h08
//
//`define HCODEC_MB_WIDTH	    8'h09
//`define HCODEC_SLICE_QP            8'h0a
//// `define HCODEC_MB_X_MB_Y           8'h0b   // current MBX and MBY                  
//`define HCODEC_PRE_START_CODE      8'h0b  // ONLY for $ucode/real/amrisc/rv.s, reg value from apollo
//`define HCODEC_SLICE_START_BYTE_01 8'h0c  // ONLY for $ucode/real/amrisc/rv.s, reg value from apollo
//`define HCODEC_SLICE_START_BYTE_23 8'h0d  // ONLY for $ucode/real/amrisc/rv.s, reg value from apollo
//`define HCODEC_RESYNC_MARKER_LENGTH 8'h0e  // Does this exist in HW ? used in $ucode/mpeg4
//
//// bit[6:5] - frame/field info, 01 - top, 10 - bottom, 11 - frame
//// bit[4:0] - buffer ID
//// L0_BUFF_ID_0, L0_BUFF_ID_1, L1_BUFF_ID_0, L1_BUFF_ID_1
//`define HCODEC_DECODER_BUFFER_INFO  8'h0f  // Current Only Used for VC1 Interlace Field
//
//`define HCODEC_FST_FOR_MV_X        8'h10
//`define HCODEC_FST_FOR_MV_Y        8'h11
//`define HCODEC_SCD_FOR_MV_X        8'h12
//`define HCODEC_SCD_FOR_MV_Y        8'h13
//`define HCODEC_FST_BAK_MV_X        8'h14
//`define HCODEC_FST_BAK_MV_Y        8'h15
//`define HCODEC_SCD_BAK_MV_X        8'h16
//`define HCODEC_SCD_BAK_MV_Y        8'h17
//
//// Bit 7:4 -- read_buffer_interlace  0-progressive, 1-interlace, used in VC1
//// bit 3 -- reserved
//// bit 2 -- weighting_prediction
//// bit 1 -- mb_weighting_flag
//// bit 0 -- slice_weighting_flag 
//`define HCODEC_VLD_DECODE_CONTROL  8'h18
//`define HCODEC_VLD_REVERVED_19     8'h19
//
//`define HCODEC_VIFF_BIT_CNT        8'h1a
//`define HCODEC_BYTE_ALIGN_PEAK_HI  8'h1b 
//`define HCODEC_BYTE_ALIGN_PEAK_LO  8'h1c
//`define HCODEC_NEXT_ALIGN_PEAK     8'h1d  // Does this exist in HW ? used in $ucode/mpeg4
//
//// bit 19    : vc1_inv_intra_co_mb_ref_rd
//// bit 18    : vc1_inv_co_mb_ref_rd
//// bit 17    : vc1_inv_intra_co_mb_ref_wr
//// bit 16    : vc1_inv_co_mb_ref_wr
//// bit 15    : reserved
//// bit 14    : avs_drop_enable
//// bit 13:12 : avs_drop_ptr
//// bit 11:8  : avs_demu_ctl_reg
//// bit 7 : avs_enable
//// bit 6 : disable_dblk_hcmd
//// bit 5 : disable_mc_hcmd
//// bit 4 : first_mode3_set enable
//// bit 3 : first_mode3
//// bit 2:1 : vc1_profile  0-SP, 1-MP, 2-reserved, 3-AP
//// bit 0   : vc1_enable
//`define HCODEC_VC1_CONTROL_REG     8'h1e
//
//`define HCODEC_PMV1_X              8'h20
//`define HCODEC_PMV1_Y              8'h21
//`define HCODEC_PMV2_X              8'h22
//`define HCODEC_PMV2_Y              8'h23
//`define HCODEC_PMV3_X              8'h24
//`define HCODEC_PMV3_Y              8'h25
//`define HCODEC_PMV4_X              8'h26
//`define HCODEC_PMV4_Y              8'h27
//// Can't use the same address for different defines
//// Therefore, create a single define HCODEC_that covers both
//// Only appears to be used in micro-code since the VLD hardware is 
//// hard coded.
//// `define HCODEC_M4_TABLE_SELECT     8'h28  // Does this exist in HW ? Added from register_mp2.h
//// `define HCODEC_M4_TABLE_OUTPUT     8'h28  // Does this exist in HW ? Added from register_mp2.h
//`define HCODEC_M4_TABLE_SELECT     8'h28  
//`define HCODEC_M4_CONTROL_REG      8'h29
//`define HCODEC_BLOCK_NUM           8'h2a  // Does this exist in HW ? Added from register_mp2.h
//`define HCODEC_PATTERN_CODE        8'h2b  // Does this exist in HW ? Added from register_mp2.h
//`define HCODEC_MB_INFO             8'h2c  // Does this exist in HW ? Added from register_mp2.h
//`define HCODEC_VLD_DC_PRED         8'h2d  // Does this exist in HW ? Added from register_mp4.h
//`define HCODEC_VLD_ERROR_MASK      8'h2e
//`define HCODEC_VLD_DC_PRED_C       8'h2f  // Does this exist in HW ? Added from register_mp4.h
//
//`define HCODEC_LAST_SLICE_MV_ADDR  8'h30
//`define HCODEC_LAST_MVX            8'h31
//`define HCODEC_LAST_MVY            8'h32
//
//`define HCODEC_VLD_C38             8'h38
//`define HCODEC_VLD_C39             8'h39
//
//`define HCODEC_VLD_STATUS          8'h3a  // Does this exist in HW ? used in $ucode/real/amrisc/rv.s
//`define HCODEC_VLD_SHIFT_STATUS    8'h3b  // Does this exist in HW ? used in $ucode/real/amrisc/rv.s
//// `define HCODEC_VLD_SHIFT_INFO      8'h3b  // Does this exist in HW ? used in $ucode/mpeg4
//`define HCODEC_VOFF_STATUS         8'h3c  // Does this exist in HW ? used in $ucode/mpeg4
//
//`define HCODEC_VLD_C3D             8'h3d
//
//`define HCODEC_VLD_DBG_INDEX       8'h3e
//
//
//// vld_buff_info -- (index == 0) 
//// Bit[7:6]  mv_UR_ready_cnt;
//// Bit[5]  vld_wr_idx
//// Bit[4]  iq_rd_idx
//// Bit[3]  vld_vi_block_rdy_1
//// Bit[2]  vld_vi_block_rdy_2
//// Bit[1]  voff_empty_1
//// Bit[0]  voff_empty_2
//
//// cabac_buff_info_0 -- (index == 1) 
//// Bit[31] shift_data_ready
//// Bit[30:29] Reserved
//// Bit[28:24] cabac_buffer_ptr
//// Bit[23:0] cabac_buffer
//
//// cabac_buff_info_1 -- (index == 2) 
//// Bit[31:29] Reserved
//// Bit[28:20] Drange
//// Bit[19:16] bin_count_4
//// Bit[15:13] Reserved
//// Bit[12:6] context_mem_do
//// Bit[5:3] coeff_state
//// Bit[2:0] mvd_state
//
//// h264_mv_present -- (index == 3) 
//// Bit[31:16] mv_present_l0
//// Bit[15:0] mv_present_l1
//
//// h264_mv_cal_info_0 -- (index == 4) 
//// [31:28] mv_cal_state
//// [27:24] direct_spatial_cnt
//// Bit[23:21] Reserved
//// Bit[20] mv_UR_ready_for_mv_cal
//// Bit[19] co_mb_mem_ready_for_mv_cal
//// Bit[18] mc_dblk_cmd_if_busy
//// Bit[17] h264_co_mb_wr_busy
//// Bit[16] H264_cbp_blk_ready
//// Bit[15] mc_hcmd_rrdy
//// Bit[14] mc_hcmd_srdy
//// Bit[13] mc_cmd_if_ready
//// Bit[12] mc_hcmd_mv_available
//// Bit[11:8] mc_cmd_if_state
//// Bit[7] dblk_hcmd_rrdy
//// Bit[6] dblk_hcmd_srdy
//// Bit[5] dblk_cmd_if_ready
//// Bit[4] dblk_hcmd_mv_available
//// Bit[3:0] dblk_cmd_if_state
//
//// h264_mv_cal_info_1 -- (index == 5) 
////  Bit[31:29] Reserved
////  Bit[28:24] total_mvd_num_l0
////  Bit[23:21] Reserved
////  Bit[20:16] mv_cal_ptr_l0
////  Bit[15:13] Reserved
////  Bit[12:8] mc_hcmd_ptr_l0
////  Bit[7:5] Reserved
////  Bit[4:0] dblk_hcmd_ptr_l0
//
//// h264_mv_cal_info_2 -- (index == 6) 
////  Bit[31:29] Reserved
////  Bit[28:24] total_mvd_num_l1
////  Bit[23:21] Reserved
////  Bit[20:16] mv_cal_ptr_l1
////  Bit[15:13] Reserved
////  Bit[12:8] mc_hcmd_ptr_l1
////  Bit[7:5] Reserved
////  Bit[4:0] dblk_hcmd_ptr_l1
//
//// h264_co_mb_info -- (index == 7)
//// Bit[31:26] Reserved
//// Bit[25] mv_scale_cal_busy
//// Bit[24:20] co_mv_count
//// Bit[19:16] co_mv_process_state
//// Bit[15] h264_co_mb_rd_busy
//// Bit[15] h264_co_mb_rd_ready
//// Bit[13:12] co_mv_transfer_block_cnt
//// Bit[11:8] co_mv_transfer_ptr
//// Bit[7] co_mv_POC_l1_busy
//// Bit[6] h264_weight_scale_cal_en
//// Bit[5] weight_cal_busy
//// Bit[4] weight_cal_not_finished
//// Bit[3:0] weight_process_state
//
//`define HCODEC_VLD_DBG_DATA        8'h3f
//// --------------------------------------------
//// VIFIFO DDR Interface
//// --------------------------------------------
//// The VIFIFO start pointer into DDR memory is a 32-bit number
//// The Start pointer will automatically be truncated to land on 
//// an 8-byte boundary.  That is, bits [2:0] = 0;
//`define HCODEC_VLD_MEM_VIFIFO_START_PTR        8'h40
//// The current pointer points so some location between the START and END 
//// pointers.  The current pointer is a BYTE pointer.  That is, you can 
//// point to any BYTE address within the START/END range
//`define HCODEC_VLD_MEM_VIFIFO_CURR_PTR         8'h41
//`define HCODEC_VLD_MEM_VIFIFO_END_PTR          8'h42
//`define HCODEC_VLD_MEM_VIFIFO_BYTES_AVAIL      8'h43
//// VIFIFO FIFO Control
//// bit  [31:24] viff_empty_int_enable_cpu[7:0] 
//// bit  [23:16] viff_empty_int_enable_amrisc[7:0] 
////   -bit 23 Video BUFFER < 0x400 Bytes
////   -bit 22 Video BUFFER < 0x200 Bytes
////   -bit 21 Video BUFFER < 0x100 Bytes
////   -bit 20 Video BUFFER < 0x80 Bytes
////   -bit 19 Video BUFFER < 0x40 Bytes
////   -bit 18 Video BUFFER < 0x20 Bytes
////   -bit 17 vififo  < 16 double words
////   -bit 16 vififo  < 8 double words
//// bit  [15:13] unused
//// bit  [12]    A_urgent
//// bit  [11]    transfer_length 0 - 32x64 Bits per request, 1 - 16x64 Bits per request
//// bit  [10]    use_level       Set this bit to 1 to enable filling of the FIFO controlled by the buffer
////                              level control.  If this bit is 0, then use bit[1] to control the enabling of filling
//// bit  [9]     Data Ready.     This bit is set when data can be popped
//// bit  [8]     fill busy       This bit will be high when we're fetching data from the DDR memory
////                              To reset this module, set cntl_enable = 0, and then wait for busy = 0. 
////                              After that you can pulse cntl_init to start over
//// bit  [7]     init_with_cntl_init
//// bit  [6]     reserved
//// bits [5:3]   endian:         see $lib/rtl/ddr_endian.v
//// bit  [2]     cntl_empty_en   Set to 1 to enable reading the DDR memory FIFO
////                              Set cntl_empty_en = cntl_fill_en = 0 when pulsing cntl_init
//// bit  [1]     cntl_fill_en    Set to 1 to enable reading data from DDR memory
//// bit  [0]     cntl_init:      After setting the read pointers, sizes, channel masks
////                              and read masks, set this bit to 1 and then to 0
////                              NOTE:  You don't need to pulse cntl_init if only the start address is
////                              being changed
//`define HCODEC_VLD_MEM_VIFIFO_CONTROL         8'h44
//// --------------------------------------------
//// VIFIFO Buffer Level Manager
//// --------------------------------------------
//`define HCODEC_VLD_MEM_VIFIFO_WP              8'h45 // Manual or Parser write pointer
//`define HCODEC_VLD_MEM_VIFIFO_RP              8'h46
//`define HCODEC_VLD_MEM_VIFIFO_LEVEL           8'h47 // must be low first to shadow low/high 16-bit words
////
//// bit  [8]     use_parser_video2_wp
//// bit  [7]     vbuf2_out_manual
//// bit  [6]     vbuf_out_manual
//// bit  [5]     empty (ReadOnly)
//// bit  [4]     full (ReadOnly)
//// bit  [3:2]   reserved
//// bit  [1]     manual mode     Set to 1 for manual write pointer mode
//// bit  [0]     Init            Set high then low after everything has been initialized
//`define HCODEC_VLD_MEM_VIFIFO_BUF_CNTL        8'h48
//
//// bit 31:16 -- drop_bytes
//// bit 15:14 -- drop_status (Read-Only)
//// bit 13:12 -- sync_match_position (Read-Only)
//// bit 11:6 -- reserved
//// bit 5:4 -- TIME_STAMP_NUMBER, 0-32bits, 1-64bits, 2-96bits, 3-128bits 
//// bit 3 -- stamp_soft_reset
//// bit 2 -- TIME_STAMP_length_enable
//// bit 1 -- TIME_STAMP_sync64_enable
//// bit 0 -- TIME_STAMP_enable
//`define HCODEC_VLD_TIME_STAMP_CNTL            8'h49
//// bit 31:0 -- TIME_STAMP_SYNC_CODE_0
//`define HCODEC_VLD_TIME_STAMP_SYNC_0          8'h4a
//// bit 31:0 -- TIME_STAMP_SYNC_CODE_1 
//`define HCODEC_VLD_TIME_STAMP_SYNC_1          8'h4b
//// bit 31:0 TIME_STAMP_0
//`define HCODEC_VLD_TIME_STAMP_0               8'h4c
//// bit 31:0 TIME_STAMP_1
//`define HCODEC_VLD_TIME_STAMP_1               8'h4d
//// bit 31:0 TIME_STAMP_2
//`define HCODEC_VLD_TIME_STAMP_2               8'h4e
//// bit 31:0 TIME_STAMP_3
//`define HCODEC_VLD_TIME_STAMP_3               8'h4f
//// bit 31:0 TIME_STAMP_LENGTH
//`define HCODEC_VLD_TIME_STAMP_LENGTH          8'h50
//
//// bit 15:0 vififo_rd_count
//`define HCODEC_VLD_MEM_VIFIFO_WRAP_COUNT      8'h51
//
//// bit 29:24 A_brst_num
//// bit 21:16 A_id
//// bit 15:0 level_hold 
//`define HCODEC_VLD_MEM_VIFIFO_MEM_CTL         8'h52
//
//`define HCODEC_VLD_MEM_VBUF_RD_PTR            8'h53 // manual read address for VBUF1
//`define HCODEC_VLD_MEM_VBUF2_RD_PTR           8'h54 // manual read address for VBUF2
//
//`define HCODEC_VLD_MEM_SWAP_ADDR              8'h55
//// bit[23:16] - swap_d_count (Read Only)
//// bit[15:8]  - swap_a_count (Read Only)
//// bit [7] - swap busy (Read Only)
//// bit [6:2] - reserved
//// bit [1] - 1 - STORE to Memory, 0 - LOAD from Memory
//// bit [0] - swap active
//`define HCODEC_VLD_MEM_SWAP_CTL               8'h56
//
// Closing file:  hcodec_vld_regs.h
//
//------------------------------------------------------------------------------
// HCODEC IQIDCT module level register offset
//------------------------------------------------------------------------------
//
// Reading file:  hcodec_iqidct_regs.h
//
//========================================================================
//  IQ/IDCT module level register offset
//========================================================================
// -----------------------------------------------
// CBUS_BASE:  DOS_HCODEC_IQIDCT_CBUS_BASE = 0x0e
// -----------------------------------------------
//
//`define HCODEC_VCOP_CTRL_REG       8'h00
//`define HCODEC_QP_CTRL_REG         8'h01
//`define HCODEC_INTRA_QUANT_MATRIX  8'h02
//`define HCODEC_NON_I_QUANT_MATRIX  8'h03
//`define HCODEC_DC_SCALER           8'h04
//`define HCODEC_DC_AC_CTRL          8'h05
//// `define HCODEC_RV_AI_CTRL          8'h05  // ONLY for $ucode/real/amrisc/rv.s reg value from apollo
//`define HCODEC_DC_AC_SCALE_MUL     8'h06
//`define HCODEC_DC_AC_SCALE_DIV     8'h07
//// `define HCODEC_DC_AC_SCALE_RESULT  8'h06
//// `define HCODEC_RESERVED_E07        8'h07
//`define HCODEC_POWER_CTL_IQIDCT    8'h08
//`define HCODEC_RV_AI_Y_X           8'h09
//`define HCODEC_RV_AI_U_X           8'h0a
//`define HCODEC_RV_AI_V_X           8'h0b
//// bit 15:0 will count up when rv_ai_mb finished when non zero
//// and rv_ai_mb_finished_int will be generate when this is not zero
//`define HCODEC_RV_AI_MB_COUNT      8'h0c
//// For H264 I in PB picture Use -- dma type : h264_next_intra_dma
//`define HCODEC_NEXT_INTRA_DMA_ADDRESS 8'h0d
//// Bit 0 -- constrained_intra_pred_flag for H264
//`define HCODEC_IQIDCT_CONTROL         8'h0e
//
//
//// Bit[31:19] Reserved
//// Bit[18] iq_waiting
//// Bit[17] iq_om_wr_idx
//// Bit[16] iq_om_rd_idx
//// Bit[15] iq_om_busy
//// Bit[14] iq_om_2_busy 
//// Bit[13] idx_fifo_0
//// Bit[12] idx_fifo_1
//// Bit[11] idx_fifo_2
//// Bit[10] idx_fifo_3
//// Bit[9] idx_fifo_4
//// Bit[8] idx_fifo_5
//// Bit[7] idx_fifo_6
//// Bit[6] idx_fifo_7
//// Bit[5:3] idx_fifo_wp
//// Bit[2:0] idx_fifo_rp
//
//`define HCODEC_IQIDCT_DEBUG_INFO_0    8'h0f
//
//// For RTL Simulation Only
//`define HCODEC_DEBLK_CMD              8'h10
//
//// Bit[15+16] ds_mc_valid_2
//// Bit[14+16] new_idct1_rd_idx_2
//// Bit[13+16] new_idct1_wr_idx_2
//// Bit[12+16] idct1_buff0_busy_2
//// Bit[11+16] idct1_buff1_busy_2
//// Bit[10+16] new_idct1_busy_2
//// Bit[9+16] iq_om_8val_2
//// Bit[8+16] idct1_pipe_busy_2
//
//// Bit[7+16] wait_mb_left_finish_hold_2
//// Bit[6+16] new_idct2_rd_idx_2
//// Bit[5+16] new_idct2_wr_idx_2
//// Bit[4+16] idct2_buff0_busy_2
//// Bit[3+16] idct2_buff1_busy_2
//// Bit[2+16] idct2_en_2
//// Bit[1+16] new_idct2_busy_2
//// Bit[0+16] new_idct1_ready_2
//
//// Bit[15] ds_mc_valid_1
//// Bit[14] new_idct1_rd_idx_1
//// Bit[13] new_idct1_wr_idx_1
//// Bit[12] idct1_buff0_busy_1
//// Bit[11] idct1_buff1_busy_1
//// Bit[10] new_idct1_busy_1
//// Bit[9] iq_om_8val_1
//// Bit[8] idct1_pipe_busy_1
//
//// Bit[7] wait_mb_left_finish_hold_1
//// Bit[6] new_idct2_rd_idx_1
//// Bit[5] new_idct2_wr_idx_1
//// Bit[4] idct2_buff0_busy_1
//// Bit[3] idct2_buff1_busy_1
//// Bit[2] idct2_en_1
//// Bit[1] new_idct2_busy_1
//// Bit[0] new_idct1_ready_1
//
//`define HCODEC_IQIDCT_DEBUG_IDCT      8'h11
//
//
//
//// bit 31 -- convas_enable
//// bit 30:24 -- convas_x_count ( 8 pixels / 64 bits )
//// bit 23:16 -- convas_y_count
//// bit 15   -- dcac_dma_busy
//// bit 14   -- dcac_dma_urgent
//// bit 13:8 -- dcac_dma_count
//// bit 7    -- dcac_dma_rw
//// bit 6    -- dcac_skip_read_mode
//// bit 5:0  -- dcac_dma_offset
//`define HCODEC_DCAC_DMA_CTRL        8'h12
//// when (convas_enable == 0 )
////   bit 31:0 dcac_dma_addr
//// when (convas_enable == 1 )
////   bit 31:25 canvas_addr (7 bits)
////   bit 24:12 convas_y_start ( 13 btis )
////   bit 11:0  convas_x_start ( 12 btis )
//`define HCODEC_DCAC_DMA_ADDRESS     8'h13
//// bit 7:0 -- dcac_cpu_addr
//`define HCODEC_DCAC_CPU_ADDRESS     8'h14
//// bit 31:0 -- dcac_cpu_data
//`define HCODEC_DCAC_CPU_DATA        8'h15
//
//// bit 31:19 -- reserved
//// bit 18:16 -- block_num_reg -- Read-Only 
//// bit 15:0 -- dcac_mb_count
//`define HCODEC_DCAC_MB_COUNT        8'h16
//
//// bit 31:18 -- reserved
//// For H264 :
////   bit 17:2 -- h264_quant 
////   bit 11:6 -- h264_quant_c 
////   bit  5:0 -- h264_quant_c 
//// For VC1 :
////   bit    17 -- qindex_GT_8
////   bit    16 -- HalfQPStep
////   bit 15:12 -- eQuantMode 
////   bit 11:6  -- AltPQuant 
////   bit  5:0  -- PQuant 
////             
//`define HCODEC_IQ_QUANT             8'h17
//
//// bit 31:24  -- bitplane_width 
//// bit 23:16  -- bitplane_height 
//// bit 15:14  -- bitplane_start_x 
//// bit 13:12  -- bitplane_start_y 
//// bit 11:4   -- reserved
//// bit 3:1    -- bitplane_type
//// bit 0      -- bitplane_busy
//`define HCODEC_VC1_BITPLANE_CTL     8'h18
//
//
//
//    `define HCODEC_RAM_TEST_CMD        12'h002
//    `define HCODEC_RAM_TEST_ADDR       12'h003
//    `define HCODEC_RAM_TEST_DATAH      12'h004
//    `define HCODEC_RAM_TEST_DATAL      12'h005
//
//    `define HCODEC_RAM_TEST_RD_CMD	    16'h0000
//    `define HCODEC_RAM_TEST_WR_CMD	    16'h8000
//    `define HCODEC_IDCT_TM2_PT0	    16'h0001
//    `define HCODEC_IDCT_TM2_PT1	    16'h0002
//    `define HCODEC_IDCT_TM1_PT0	    16'h0004
//    `define HCODEC_IDCT_TM1_PT1	    16'h0008
//    `define HCODEC_IQ_OMEM_PT0	        16'h0010
//    `define HCODEC_IQ_OMEM_PT1	        16'h0020
//    `define HCODEC_MC_IMEM_PT0	        16'h0040
//    `define HCODEC_ALL_RAM_PTS	        16'h007f
//
////======================================
////  VCOP Control Register Bits
////
////======================================
//    //`define HCODEC_IQIDCT_RESET	    16'h0001	    // Bit 0
//    `define HCODEC_QM_WEN		    16'h0002	    // Bit 1
//    `define HCODEC_IQIDCT_ENABLE	    16'h0004	    // Bit 2
//    `define HCODEC_INTRA_QM	    16'h0008	    // Bit 3	0 = Use default; 1 = use loaded
//    `define HCODEC_NINTRA_QM	    16'h0010	    // Bit 4	0 = Use default; 1 = use loaded
//
////======================================
////  QP Control Register Bits
////
////======================================
//    `define HCODEC_INTRA_MODE	    16'h0080	    // Bit 7
//// Duplicate Address:  When actually used
//// please move to a different address
//// `define HCODEC_FLD_DCT_TYPE	    16'h0100	    // Bit 8	0 = Frame DCT; 1 = field DCT
//
//
// Closing file:  hcodec_iqidct_regs.h
//
//------------------------------------------------------------------------------
// HCODEC IQIDCT module level register offset
//------------------------------------------------------------------------------
//
// Reading file:  hcodec_vcpu_regs.h
//
//========================================================================
//  VCPU module level register offset
//========================================================================
// -----------------------------------------------
// CBUS_BASE:  DOS_HCODEC_VCPU_CBUS_BASE = 0x03
// -----------------------------------------------
//`define HCODEC_MSP                 8'h00
//`define HCODEC_MPSR                8'h01
//`define HCODEC_MINT_VEC_BASE       8'h02
//`define HCODEC_MCPU_INTR_GRP       8'h03
//`define HCODEC_MCPU_INTR_MSK       8'h04
//`define HCODEC_MCPU_INTR_REQ       8'h05
//`define HCODEC_MPC_P               8'h06
//`define HCODEC_MPC_D               8'h07
//`define HCODEC_MPC_E			    8'h08
//`define HCODEC_MPC_W			    8'h09
//`define HCODEC_MINDEX0_REG			8'h0a
//`define HCODEC_MINDEX1_REG			8'h0b
//`define HCODEC_MINDEX2_REG			8'h0c
//`define HCODEC_MINDEX3_REG			8'h0d
//`define HCODEC_MINDEX4_REG			8'h0e
//`define HCODEC_MINDEX5_REG			8'h0f
//`define HCODEC_MINDEX6_REG			8'h10
//`define HCODEC_MINDEX7_REG			8'h11
//`define HCODEC_MMIN_REG			8'h12
//`define HCODEC_MMAX_REG			8'h13
//`define HCODEC_MBREAK0_REG			8'h14
//`define HCODEC_MBREAK1_REG			8'h15
//`define HCODEC_MBREAK2_REG			8'h16
//`define HCODEC_MBREAK3_REG			8'h17
//`define HCODEC_MBREAK_TYPE			8'h18
//`define HCODEC_MBREAK_CTRL			8'h19
//`define HCODEC_MBREAK_STAUTS		8'h1a
//`define HCODEC_MDB_ADDR_REG		8'h1b
//`define HCODEC_MDB_DATA_REG		8'h1c
//`define HCODEC_MDB_CTRL			8'h1d
//`define HCODEC_MSFTINT0            8'h1e
//`define HCODEC_MSFTINT1            8'h1f
//
//`define HCODEC_CSP                 8'h20
//`define HCODEC_CPSR                8'h21
//`define HCODEC_CINT_VEC_BASE       8'h22
//`define HCODEC_CCPU_INTR_GRP       8'h23
//`define HCODEC_CCPU_INTR_MSK       8'h24
//`define HCODEC_CCPU_INTR_REQ       8'h25
//`define HCODEC_CPC_P               8'h26
//`define HCODEC_CPC_D               8'h27
//`define HCODEC_CPC_E			    8'h28
//`define HCODEC_CPC_W			    8'h29
//`define HCODEC_CINDEX0_REG			8'h2a
//`define HCODEC_CINDEX1_REG			8'h2b
//`define HCODEC_CINDEX2_REG			8'h2c
//`define HCODEC_CINDEX3_REG			8'h2d
//`define HCODEC_CINDEX4_REG			8'h2e
//`define HCODEC_CINDEX5_REG			8'h2f
//`define HCODEC_CINDEX6_REG			8'h30
//`define HCODEC_CINDEX7_REG			8'h31
//`define HCODEC_CMIN_REG			8'h32
//`define HCODEC_CMAX_REG			8'h33
//`define HCODEC_CBREAK0_REG			8'h34
//`define HCODEC_CBREAK1_REG			8'h35
//`define HCODEC_CBREAK2_REG			8'h36
//`define HCODEC_CBREAK3_REG			8'h37
//`define HCODEC_CBREAK_TYPE			8'h38
//`define HCODEC_CBREAK_CTRL			8'h39
//`define HCODEC_CBREAK_STAUTS		8'h3a
//`define HCODEC_CDB_ADDR_REG		8'h3b
//`define HCODEC_CDB_DATA_REG		8'h3c
//`define HCODEC_CDB_CTRL			8'h3d
//`define HCODEC_CSFTINT0            8'h3e
//`define HCODEC_CSFTINT1            8'h3f
//
//`define HCODEC_IMEM_DMA_CTRL       8'h40
//`define HCODEC_IMEM_DMA_ADR        8'h41
//`define HCODEC_IMEM_DMA_COUNT      8'h42
//// bit[29:24] A_brst_num_imem
//// bit[21:16] A_id_imem
//// bit[11:0] wrrsp_count_imem (reserved)
//`define HCODEC_WRRSP_IMEM          8'h43
//
//`define HCODEC_LMEM_DMA_CTRL       8'h50
//`define HCODEC_LMEM_DMA_ADR        8'h51
//`define HCODEC_LMEM_DMA_COUNT      8'h52
//// bit[29:24] A_brst_num_lmem
//// bit[21:16] A_id_lmem
//// bit[11:0] wrrsp_count_lmem 
//`define HCODEC_WRRSP_LMEM          8'h53
//
//`define HCODEC_MAC_CTRL1			8'h60
//`define HCODEC_ACC0REG1			8'h61
//`define HCODEC_ACC1REG1			8'h62
//
//`define HCODEC_MAC_CTRL2			8'h70
//`define HCODEC_ACC0REG2			8'h71
//`define HCODEC_ACC1REG2			8'h72
//`define HCODEC_CPU_TRACE			8'h80
//
//
// Closing file:  hcodec_vcpu_regs.h
//
//------------------------------------------------------------------------------
//  DOS top-level register offset
//------------------------------------------------------------------------------
// -----------------------------------------------
// CBUS_BASE:  DOS_TOP_CBUS_BASE = 0x3f
// -----------------------------------------------
#define DOS_SW_RESET0                              0x3f00
#define DOS_GCLK_EN0                               0x3f01
#define DOS_GEN_CTRL0                              0x3f02
#define DOS_APB_ERR_CTRL                           0x3f03
#define DOS_APB_ERR_STAT                           0x3f04
#define DOS_VDEC_INT_EN                            0x3f05
#define DOS_HCODEC_INT_EN                          0x3f06
#define DOS_SW_RESET1                              0x3f07
#define DOS_SW_RESET2                              0x3f08
#define DOS_GCLK_EN1                               0x3f09
#define DOS_VDEC2_INT_EN                           0x3f0a
#define DOS_VDIN_LCNT                              0x3f0b
#define DOS_VDIN_FCNT                              0x3f0c
#define DOS_VDIN_CCTL                              0x3f0d
#define DOS_SCRATCH0                               0x3f10
#define DOS_SCRATCH1                               0x3f11
#define DOS_SCRATCH2                               0x3f12
#define DOS_SCRATCH3                               0x3f13
#define DOS_SCRATCH4                               0x3f14
#define DOS_SCRATCH5                               0x3f15
#define DOS_SCRATCH6                               0x3f16
#define DOS_SCRATCH7                               0x3f17
#define DOS_SCRATCH8                               0x3f18
#define DOS_SCRATCH9                               0x3f19
#define DOS_SCRATCH10                              0x3f1a
#define DOS_SCRATCH11                              0x3f1b
#define DOS_SCRATCH12                              0x3f1c
#define DOS_SCRATCH13                              0x3f1d
#define DOS_SCRATCH14                              0x3f1e
#define DOS_SCRATCH15                              0x3f1f
#define DOS_SCRATCH16                              0x3f20
#define DOS_SCRATCH17                              0x3f21
#define DOS_SCRATCH18                              0x3f22
#define DOS_SCRATCH19                              0x3f23
#define DOS_SCRATCH20                              0x3f24
#define DOS_SCRATCH21                              0x3f25
#define DOS_SCRATCH22                              0x3f26
#define DOS_SCRATCH23                              0x3f27
#define DOS_SCRATCH24                              0x3f28
#define DOS_SCRATCH25                              0x3f29
#define DOS_SCRATCH26                              0x3f2a
#define DOS_SCRATCH27                              0x3f2b
#define DOS_SCRATCH28                              0x3f2c
#define DOS_SCRATCH29                              0x3f2d
#define DOS_SCRATCH30                              0x3f2e
#define DOS_SCRATCH31                              0x3f2f
#define DOS_MEM_PD_VDEC                            0x3f30
#define DOS_MEM_PD_VDEC2                           0x3f31
#define DOS_MEM_PD_HCODEC                          0x3f32
// bit[31]    mcrcc_stall_en
// bit[30:28] Reserved
// bit[27:20] target_canvas
// bit[19:10] target_mby
// bit[ 9: 0] target_mbx
#define DOS_VDEC_MCRCC_STALL_CTRL                  0x3f40
#define DOS_VDEC_MCRCC_STALL2_CTRL                 0x3f42
#define DOS_VDEC2_MCRCC_STALL_CTRL                 0x3f41
#define DOS_VDEC2_MCRCC_STALL2_CTRL                0x3f43
//
// Closing file:  ./dos_param.h
//
//
// Reading file:  mdec_regs.h
//
//========================================================================
//  MDEC module level register offset
//========================================================================
// -----------------------------------------------
// CBUS_BASE:  DOS_VDEC_MDEC_CBUS_BASE = 0x09
// -----------------------------------------------
#define HCODEC_MC_CTRL_REG                         0x0900
#define HCODEC_MC_MB_INFO                          0x0901
#define HCODEC_MC_PIC_INFO                         0x0902
#define HCODEC_MC_HALF_PEL_ONE                     0x0903
#define HCODEC_MC_HALF_PEL_TWO                     0x0904
#define HCODEC_POWER_CTL_MC                        0x0905
#define HCODEC_MC_CMD                              0x0906
#define HCODEC_MC_CTRL0                            0x0907
#define HCODEC_MC_PIC_W_H                          0x0908
#define HCODEC_MC_STATUS0                          0x0909
#define HCODEC_MC_STATUS1                          0x090a
#define HCODEC_MC_CTRL1                            0x090b
#define HCODEC_MC_MIX_RATIO0                       0x090c
#define HCODEC_MC_MIX_RATIO1                       0x090d
#define HCODEC_MC_DP_MB_XY                         0x090e
#define HCODEC_MC_OM_MB_XY                         0x090f
#define HCODEC_PSCALE_RST                          0x0910
#define HCODEC_PSCALE_CTRL                         0x0911
#define HCODEC_PSCALE_PICI_W                       0x0912
#define HCODEC_PSCALE_PICI_H                       0x0913
#define HCODEC_PSCALE_PICO_W                       0x0914
#define HCODEC_PSCALE_PICO_H                       0x0915
#define HCODEC_PSCALE_PICO_START_X                 0x0916
#define HCODEC_PSCALE_PICO_START_Y                 0x0917
#define HCODEC_PSCALE_DUMMY                        0x0918
#define HCODEC_PSCALE_FILT0_COEF0                  0x0919
#define HCODEC_PSCALE_FILT0_COEF1                  0x091a
#define HCODEC_PSCALE_CMD_CTRL                     0x091b
#define HCODEC_PSCALE_CMD_BLK_X                    0x091c
#define HCODEC_PSCALE_CMD_BLK_Y                    0x091d
#define HCODEC_PSCALE_STATUS                       0x091e
#define HCODEC_PSCALE_BMEM_ADDR                    0x091f
#define HCODEC_PSCALE_BMEM_DAT                     0x0920
#define HCODEC_PSCALE_DRAM_BUF_CTRL                0x0921
#define HCODEC_PSCALE_MCMD_CTRL                    0x0922
#define HCODEC_PSCALE_MCMD_XSIZE                   0x0923
#define HCODEC_PSCALE_MCMD_YSIZE                   0x0924
#define HCODEC_PSCALE_RBUF_START_BLKX              0x0925
#define HCODEC_PSCALE_RBUF_START_BLKY              0x0926
//`define PSCALE_RBUF_MB_WIDTH   8'h27
#define HCODEC_PSCALE_PICO_SHIFT_XY                0x0928
#define HCODEC_PSCALE_CTRL1                        0x0929
//Bit 15, wmask enable
//Bit 14:13, filt0 srckey_less, 
//Bit 12:11, filt1 srckey_less, in the case of the interpolated data is equal distance to 
//key data and normal data, 00: select normal data, 01: select right data, 10: select key data
//Bit 10:9, srckey mode, 00: equal, 01: less than or equal, 10: great than or equal
//Bit 8, src key enable
//Bit 7:0, y src key
#define HCODEC_PSCALE_SRCKEY_CTRL0                 0x092a
//Bit 15:8, cb src key
//Bit 7:0, cr src key
#define HCODEC_PSCALE_SRCKEY_CTRL1                 0x092b
//Bit 22:16 canvas_rd_addr2
//Bit 14:8 canvas_rd_addr1
//Bit 6:0 canvas_rd_addr1
#define HCODEC_PSCALE_CANVAS_RD_ADDR               0x092c
//Bit 22:16 canvas_wr_addr2
//Bit 14:8 canvas_wr_addr1
//Bit 6:0 canvas_wr_addr1
#define HCODEC_PSCALE_CANVAS_WR_ADDR               0x092d
//bit 13:8 pscale thread ID and token 
//bit 7 disable write response count adding to busy bit 
//bit 5:0  pscale prearbitor burst num
#define HCODEC_PSCALE_CTRL2                        0x092e
#define HCODEC_MC_MPORT_CTRL                       0x0940
#define HCODEC_MC_MPORT_DAT                        0x0941
#define HCODEC_MC_WT_PRED_CTRL                     0x0942
#define HCODEC_MC_MBBOT_ST_EVEN_ADDR               0x0944
#define HCODEC_MC_MBBOT_ST_ODD_ADDR                0x0945
#define HCODEC_MC_DPDN_MB_XY                       0x0946
#define HCODEC_MC_OMDN_MB_XY                       0x0947
#define HCODEC_MC_HCMDBUF_H                        0x0948
#define HCODEC_MC_HCMDBUF_L                        0x0949
#define HCODEC_MC_HCMD_H                           0x094a
#define HCODEC_MC_HCMD_L                           0x094b
#define HCODEC_MC_IDCT_DAT                         0x094c
#define HCODEC_MC_CTRL_GCLK_CTRL                   0x094d
#define HCODEC_MC_OTHER_GCLK_CTRL                  0x094e
//Bit 29:24, mbbot thread ID and token 
//Bit 21:16, mc read/write thread ID and token 
//Bit 13:8,  mbbot pre-arbitor burst number 
//Bit 5:0,   mc pre-arbitor burst number 
#define HCODEC_MC_CTRL2                            0x094f
// `define DBLK_QUANT            8'h76 // ONLY for $ucode/real/amrisc/rv.s, reg value from apollo
//`define ANC1_CANVAS_ADDR      8'h80
//`define ANC2_CANVAS_ADDR      8'h81
//`define REC_CANVAS_ADDR       8'h89
//`define MDEC_PIC_W          8'h8c
//`define MDEC_PIC_H          8'h8d
#define HCODEC_MDEC_PIC_DC_CTRL                    0x098e
#define HCODEC_MDEC_PIC_DC_STATUS                  0x098f
#define HCODEC_ANC0_CANVAS_ADDR                    0x0990
#define HCODEC_ANC1_CANVAS_ADDR                    0x0991
#define HCODEC_ANC2_CANVAS_ADDR                    0x0992
#define HCODEC_ANC3_CANVAS_ADDR                    0x0993
#define HCODEC_ANC4_CANVAS_ADDR                    0x0994
#define HCODEC_ANC5_CANVAS_ADDR                    0x0995
#define HCODEC_ANC6_CANVAS_ADDR                    0x0996
#define HCODEC_ANC7_CANVAS_ADDR                    0x0997
#define HCODEC_ANC8_CANVAS_ADDR                    0x0998
#define HCODEC_ANC9_CANVAS_ADDR                    0x0999
#define HCODEC_ANC10_CANVAS_ADDR                   0x099a
#define HCODEC_ANC11_CANVAS_ADDR                   0x099b
#define HCODEC_ANC12_CANVAS_ADDR                   0x099c
#define HCODEC_ANC13_CANVAS_ADDR                   0x099d
#define HCODEC_ANC14_CANVAS_ADDR                   0x099e
#define HCODEC_ANC15_CANVAS_ADDR                   0x099f
#define HCODEC_ANC16_CANVAS_ADDR                   0x09a0
#define HCODEC_ANC17_CANVAS_ADDR                   0x09a1
#define HCODEC_ANC18_CANVAS_ADDR                   0x09a2
#define HCODEC_ANC19_CANVAS_ADDR                   0x09a3
#define HCODEC_ANC20_CANVAS_ADDR                   0x09a4
#define HCODEC_ANC21_CANVAS_ADDR                   0x09a5
#define HCODEC_ANC22_CANVAS_ADDR                   0x09a6
#define HCODEC_ANC23_CANVAS_ADDR                   0x09a7
#define HCODEC_ANC24_CANVAS_ADDR                   0x09a8
#define HCODEC_ANC25_CANVAS_ADDR                   0x09a9
#define HCODEC_ANC26_CANVAS_ADDR                   0x09aa
#define HCODEC_ANC27_CANVAS_ADDR                   0x09ab
#define HCODEC_ANC28_CANVAS_ADDR                   0x09ac
#define HCODEC_ANC29_CANVAS_ADDR                   0x09ad
#define HCODEC_ANC30_CANVAS_ADDR                   0x09ae
#define HCODEC_ANC31_CANVAS_ADDR                   0x09af
#define HCODEC_DBKR_CANVAS_ADDR                    0x09b0
#define HCODEC_DBKW_CANVAS_ADDR                    0x09b1
#define HCODEC_REC_CANVAS_ADDR                     0x09b2
//28:24, read/write, current canvas idx, used in h264 only now
//23:0, read only, current canvas address, 23:16, Cr canvas addr, 15:8, Cb canvas addr, 7:0, Y  canvas addr
#define HCODEC_CURR_CANVAS_CTRL                    0x09b3
#define HCODEC_MDEC_PIC_DC_THRESH                  0x09b8
#define HCODEC_MDEC_PICR_BUF_STATUS                0x09b9
#define HCODEC_MDEC_PICW_BUF_STATUS                0x09ba
#define HCODEC_MCW_DBLK_WRRSP_CNT                  0x09bb
#define HCODEC_MC_MBBOT_WRRSP_CNT                  0x09bc
#define HCODEC_MDEC_PICW_BUF2_STATUS               0x09bd
#define HCODEC_WRRSP_FIFO_PICW_DBK                 0x09be
#define HCODEC_WRRSP_FIFO_PICW_MC                  0x09bf
#define HCODEC_AV_SCRATCH_0                        0x09c0
#define HCODEC_AV_SCRATCH_1                        0x09c1
#define HCODEC_AV_SCRATCH_2                        0x09c2
#define HCODEC_AV_SCRATCH_3                        0x09c3
#define HCODEC_AV_SCRATCH_4                        0x09c4
#define HCODEC_AV_SCRATCH_5                        0x09c5
#define HCODEC_AV_SCRATCH_6                        0x09c6
#define HCODEC_AV_SCRATCH_7                        0x09c7
#define HCODEC_AV_SCRATCH_8                        0x09c8
#define HCODEC_AV_SCRATCH_9                        0x09c9
#define HCODEC_AV_SCRATCH_A                        0x09ca
#define HCODEC_AV_SCRATCH_B                        0x09cb
#define HCODEC_AV_SCRATCH_C                        0x09cc
#define HCODEC_AV_SCRATCH_D                        0x09cd
#define HCODEC_AV_SCRATCH_E                        0x09ce
#define HCODEC_AV_SCRATCH_F                        0x09cf
#define HCODEC_AV_SCRATCH_G                        0x09d0
#define HCODEC_AV_SCRATCH_H                        0x09d1
#define HCODEC_AV_SCRATCH_I                        0x09d2
#define HCODEC_AV_SCRATCH_J                        0x09d3
#define HCODEC_AV_SCRATCH_K                        0x09d4
#define HCODEC_AV_SCRATCH_L                        0x09d5
#define HCODEC_AV_SCRATCH_M                        0x09d6
#define HCODEC_AV_SCRATCH_N                        0x09d7
// bit[29:24] A_brst_num_co_mb
// bit[21:16] A_id_co_mb
// bit[11:0] wrrsp_count_co_mb
#define HCODEC_WRRSP_CO_MB                         0x09d8
// bit[29:24] A_brst_num_dcac
// bit[21:16] A_id_dcac
// bit[11:0] wrrsp_count_dcac
#define HCODEC_WRRSP_DCAC                          0x09d9
//======================================
//  MC Control Register Bits
//
//======================================
// For bits, just copy the defines...don't translate to addresses
    //`define MC_RESET	    16'h0002
//======================================
//  MB Info Register Bits
//
//======================================
//======================================
//  MB Info Register Bits
//
//======================================
//========================================================================
// DBLK Register:  12'h950 - 12'h97f 
//========================================================================
#define HCODEC_DBLK_RST                            0x0950
#define HCODEC_DBLK_CTRL                           0x0951
#define HCODEC_DBLK_MB_WID_HEIGHT                  0x0952
#define HCODEC_DBLK_STATUS                         0x0953
#define HCODEC_DBLK_CMD_CTRL                       0x0954
#define HCODEC_DBLK_MB_XY                          0x0955
#define HCODEC_DBLK_QP                             0x0956
#define HCODEC_DBLK_Y_BHFILT                       0x0957
#define HCODEC_DBLK_Y_BHFILT_HIGH                  0x0958
#define HCODEC_DBLK_Y_BVFILT                       0x0959
#define HCODEC_DBLK_CB_BFILT                       0x095a
#define HCODEC_DBLK_CR_BFILT                       0x095b
#define HCODEC_DBLK_Y_HFILT                        0x095c
#define HCODEC_DBLK_Y_HFILT_HIGH                   0x095d
#define HCODEC_DBLK_Y_VFILT                        0x095e
#define HCODEC_DBLK_CB_FILT                        0x095f
#define HCODEC_DBLK_CR_FILT                        0x0960
#define HCODEC_DBLK_BETAX_QP_SEL                   0x0961
#define HCODEC_DBLK_CLIP_CTRL0                     0x0962
#define HCODEC_DBLK_CLIP_CTRL1                     0x0963
#define HCODEC_DBLK_CLIP_CTRL2                     0x0964
#define HCODEC_DBLK_CLIP_CTRL3                     0x0965
#define HCODEC_DBLK_CLIP_CTRL4                     0x0966
#define HCODEC_DBLK_CLIP_CTRL5                     0x0967
#define HCODEC_DBLK_CLIP_CTRL6                     0x0968
#define HCODEC_DBLK_CLIP_CTRL7                     0x0969
#define HCODEC_DBLK_CLIP_CTRL8                     0x096a
#define HCODEC_DBLK_STATUS1                        0x096b
#define HCODEC_DBLK_GCLK_FREE                      0x096c
#define HCODEC_DBLK_GCLK_OFF                       0x096d
#define HCODEC_DBLK_AVSFLAGS                       0x096e
// bit 15:0
#define HCODEC_DBLK_CBPY                           0x0970
// bit 11:8 -- deblk_cbpy_bottom
// bit 7:4 -- deblk_cbpy_left
// bit 3:0 -- deblk_cbpy_top
#define HCODEC_DBLK_CBPY_ADJ                       0x0971
// bit 7:0 -- deblk_cbpc
#define HCODEC_DBLK_CBPC                           0x0972
// bit 15 -- bottom_mb
// bit 14 -- left_mb
// bit 13 -- top_mb
// bit 12 -- reserved
// bit 11:8 -- deblk_cbpc_bottom
// bit 7:4 -- deblk_cbpc_left
// bit 3:0 -- deblk_cbpc_top
#define HCODEC_DBLK_CBPC_ADJ                       0x0973
// bit 15:8 -- deblk_hmvd   -- {left_1, left_0, below_1, below_0, block3-0} 
// bit 7:0 -- deblk_vmvd    -- {top_1, top_0, below_1, below_0, block3-0} 
#define HCODEC_DBLK_VHMVD                          0x0974
// bit 13:12 -- right_vmvd
// bit 11 -- right_above_vmvd
// bit 10 -- left_below_hmvd
// bit 9 -- disable_dblk_luma  
// bit 8 -- disable_dblk_chroma
// bit 7 -- bBelowRefDiff
// bit 6 -- bLeftRefDiff
// bit 5 -- bAboveRefDiff
// bit 4 -- reserved
// bit 3 -- s_below
// bit 2 -- s_left
// bit 1 -- s_above
// bit 0 -- s 
#define HCODEC_DBLK_STRONG                         0x0975
// bit 14:10 -- PQUANT 
// bit 9:5 -- left_PQUANT 
// bit 4:0 -- top_PQUANT 
#define HCODEC_DBLK_RV8_QUANT                      0x0976
#define HCODEC_DBLK_CBUS_HCMD2                     0x0977
#define HCODEC_DBLK_CBUS_HCMD1                     0x0978
#define HCODEC_DBLK_CBUS_HCMD0                     0x0979
#define HCODEC_DBLK_VLD_HCMD2                      0x097a
#define HCODEC_DBLK_VLD_HCMD1                      0x097b
#define HCODEC_DBLK_VLD_HCMD0                      0x097c
#define HCODEC_DBLK_OST_YBASE                      0x097d
#define HCODEC_DBLK_OST_CBCRDIFF                   0x097e
//13:8 dblk thread ID and token 
//5:0  dblk prearbitor burst num
#define HCODEC_DBLK_CTRL1                          0x097f
// MCRCC_CTL1
// 31:3  <reserved[23:0]>
// 2     <cfg_field_pic>
// 1     <sw_rst>
// 0     <bypass_en>
#define HCODEC_MCRCC_CTL1                          0x0980
// MCRCC_CTL2
// 31:24    <cfg_cache_anc01_c[7:0]>
// 23:16    <cfg_cache_anc01_y[7:0]>
// 15:8     <cfg_cache_anc00_c[7:0]>
// 7:0      <cfg_cache_anc00_y[7:0]>
#define HCODEC_MCRCC_CTL2                          0x0981
// MCRCC_CTL3
// 31:24    <cfg_cache_anc11_c[7:0]>
// 23:16    <cfg_cache_anc11_y[7:0]>
// 15:8     <cfg_cache_anc10_c[7:0]>
// 7:0      <cfg_cache_anc10_y[7:0]>
#define HCODEC_MCRCC_CTL3                          0x0982
// bit[31:10] reserved
// bit[9:0] sw_clock_gating control 
// [9] vdec clk_en for assist and cbus.
// [8] vdec clk_en for ddr
// [7] vdec clk_en for vcpu
// [6] vdec clk_en for assist
// [5] vdec clk_en for dblk
// [4] vdec clk_en for iqidct
// [3] vdec clk_en for mc
// [2] vdec clk_en for pic_dc
// [1] vdec clk_en for psc
// [0] vdec clk_en for vld
#define HCODEC_GCLK_EN                             0x0983
// [0]  Reserved 
// [1]  Reserved
// [2]  Reset assist, mdec's CBUS
// [3]  Reset mdec's VLD
// [4]  Reset mdec's VLD
// [5]  Reset mdec's VLD
// [6]  Reset mdec's IQIDCT
// [7]  Reset mdec's MC
// [8]  Reset mdec's DBLK
// [9]  Reset mdec's PIC_DC
// [10] Reset mdec's Pscale
// [11] Reset vcpu's MCPU
// [12] Reset vcpu's CCPU
// [13] Reset mmc_pre_arb
#define HCODEC_MDEC_SW_RESET                       0x0984
//DBLK last address 12'h97f
//
// Closing file:  mdec_regs.h
//
//
// Reading file:  mdec_regs.h
//
//========================================================================
//  MDEC module level register offset
//========================================================================
// -----------------------------------------------
// CBUS_BASE:  DOS_VDEC_MDEC_CBUS_BASE = 0x09
// -----------------------------------------------
#define VDEC2_MC_CTRL_REG                          0x0900
#define VDEC2_MC_MB_INFO                           0x0901
#define VDEC2_MC_PIC_INFO                          0x0902
#define VDEC2_MC_HALF_PEL_ONE                      0x0903
#define VDEC2_MC_HALF_PEL_TWO                      0x0904
#define VDEC2_POWER_CTL_MC                         0x0905
#define VDEC2_MC_CMD                               0x0906
#define VDEC2_MC_CTRL0                             0x0907
#define VDEC2_MC_PIC_W_H                           0x0908
#define VDEC2_MC_STATUS0                           0x0909
#define VDEC2_MC_STATUS1                           0x090a
#define VDEC2_MC_CTRL1                             0x090b
#define VDEC2_MC_MIX_RATIO0                        0x090c
#define VDEC2_MC_MIX_RATIO1                        0x090d
#define VDEC2_MC_DP_MB_XY                          0x090e
#define VDEC2_MC_OM_MB_XY                          0x090f
#define VDEC2_PSCALE_RST                           0x0910
#define VDEC2_PSCALE_CTRL                          0x0911
#define VDEC2_PSCALE_PICI_W                        0x0912
#define VDEC2_PSCALE_PICI_H                        0x0913
#define VDEC2_PSCALE_PICO_W                        0x0914
#define VDEC2_PSCALE_PICO_H                        0x0915
#define VDEC2_PSCALE_PICO_START_X                  0x0916
#define VDEC2_PSCALE_PICO_START_Y                  0x0917
#define VDEC2_PSCALE_DUMMY                         0x0918
#define VDEC2_PSCALE_FILT0_COEF0                   0x0919
#define VDEC2_PSCALE_FILT0_COEF1                   0x091a
#define VDEC2_PSCALE_CMD_CTRL                      0x091b
#define VDEC2_PSCALE_CMD_BLK_X                     0x091c
#define VDEC2_PSCALE_CMD_BLK_Y                     0x091d
#define VDEC2_PSCALE_STATUS                        0x091e
#define VDEC2_PSCALE_BMEM_ADDR                     0x091f
#define VDEC2_PSCALE_BMEM_DAT                      0x0920
#define VDEC2_PSCALE_DRAM_BUF_CTRL                 0x0921
#define VDEC2_PSCALE_MCMD_CTRL                     0x0922
#define VDEC2_PSCALE_MCMD_XSIZE                    0x0923
#define VDEC2_PSCALE_MCMD_YSIZE                    0x0924
#define VDEC2_PSCALE_RBUF_START_BLKX               0x0925
#define VDEC2_PSCALE_RBUF_START_BLKY               0x0926
//`define PSCALE_RBUF_MB_WIDTH   8'h27
#define VDEC2_PSCALE_PICO_SHIFT_XY                 0x0928
#define VDEC2_PSCALE_CTRL1                         0x0929
//Bit 15, wmask enable
//Bit 14:13, filt0 srckey_less, 
//Bit 12:11, filt1 srckey_less, in the case of the interpolated data is equal distance to 
//key data and normal data, 00: select normal data, 01: select right data, 10: select key data
//Bit 10:9, srckey mode, 00: equal, 01: less than or equal, 10: great than or equal
//Bit 8, src key enable
//Bit 7:0, y src key
#define VDEC2_PSCALE_SRCKEY_CTRL0                  0x092a
//Bit 15:8, cb src key
//Bit 7:0, cr src key
#define VDEC2_PSCALE_SRCKEY_CTRL1                  0x092b
//Bit 22:16 canvas_rd_addr2
//Bit 14:8 canvas_rd_addr1
//Bit 6:0 canvas_rd_addr1
#define VDEC2_PSCALE_CANVAS_RD_ADDR                0x092c
//Bit 22:16 canvas_wr_addr2
//Bit 14:8 canvas_wr_addr1
//Bit 6:0 canvas_wr_addr1
#define VDEC2_PSCALE_CANVAS_WR_ADDR                0x092d
//bit 13:8 pscale thread ID and token 
//bit 7 disable write response count adding to busy bit 
//bit 5:0  pscale prearbitor burst num
#define VDEC2_PSCALE_CTRL2                         0x092e
#define VDEC2_MC_MPORT_CTRL                        0x0940
#define VDEC2_MC_MPORT_DAT                         0x0941
#define VDEC2_MC_WT_PRED_CTRL                      0x0942
#define VDEC2_MC_MBBOT_ST_EVEN_ADDR                0x0944
#define VDEC2_MC_MBBOT_ST_ODD_ADDR                 0x0945
#define VDEC2_MC_DPDN_MB_XY                        0x0946
#define VDEC2_MC_OMDN_MB_XY                        0x0947
#define VDEC2_MC_HCMDBUF_H                         0x0948
#define VDEC2_MC_HCMDBUF_L                         0x0949
#define VDEC2_MC_HCMD_H                            0x094a
#define VDEC2_MC_HCMD_L                            0x094b
#define VDEC2_MC_IDCT_DAT                          0x094c
#define VDEC2_MC_CTRL_GCLK_CTRL                    0x094d
#define VDEC2_MC_OTHER_GCLK_CTRL                   0x094e
//Bit 29:24, mbbot thread ID and token 
//Bit 21:16, mc read/write thread ID and token 
//Bit 13:8,  mbbot pre-arbitor burst number 
//Bit 5:0,   mc pre-arbitor burst number 
#define VDEC2_MC_CTRL2                             0x094f
// `define DBLK_QUANT            8'h76 // ONLY for $ucode/real/amrisc/rv.s, reg value from apollo
//`define ANC1_CANVAS_ADDR      8'h80
//`define ANC2_CANVAS_ADDR      8'h81
//`define REC_CANVAS_ADDR       8'h89
//`define MDEC_PIC_W          8'h8c
//`define MDEC_PIC_H          8'h8d
#define VDEC2_MDEC_PIC_DC_CTRL                     0x098e
#define VDEC2_MDEC_PIC_DC_STATUS                   0x098f
#define VDEC2_ANC0_CANVAS_ADDR                     0x0990
#define VDEC2_ANC1_CANVAS_ADDR                     0x0991
#define VDEC2_ANC2_CANVAS_ADDR                     0x0992
#define VDEC2_ANC3_CANVAS_ADDR                     0x0993
#define VDEC2_ANC4_CANVAS_ADDR                     0x0994
#define VDEC2_ANC5_CANVAS_ADDR                     0x0995
#define VDEC2_ANC6_CANVAS_ADDR                     0x0996
#define VDEC2_ANC7_CANVAS_ADDR                     0x0997
#define VDEC2_ANC8_CANVAS_ADDR                     0x0998
#define VDEC2_ANC9_CANVAS_ADDR                     0x0999
#define VDEC2_ANC10_CANVAS_ADDR                    0x099a
#define VDEC2_ANC11_CANVAS_ADDR                    0x099b
#define VDEC2_ANC12_CANVAS_ADDR                    0x099c
#define VDEC2_ANC13_CANVAS_ADDR                    0x099d
#define VDEC2_ANC14_CANVAS_ADDR                    0x099e
#define VDEC2_ANC15_CANVAS_ADDR                    0x099f
#define VDEC2_ANC16_CANVAS_ADDR                    0x09a0
#define VDEC2_ANC17_CANVAS_ADDR                    0x09a1
#define VDEC2_ANC18_CANVAS_ADDR                    0x09a2
#define VDEC2_ANC19_CANVAS_ADDR                    0x09a3
#define VDEC2_ANC20_CANVAS_ADDR                    0x09a4
#define VDEC2_ANC21_CANVAS_ADDR                    0x09a5
#define VDEC2_ANC22_CANVAS_ADDR                    0x09a6
#define VDEC2_ANC23_CANVAS_ADDR                    0x09a7
#define VDEC2_ANC24_CANVAS_ADDR                    0x09a8
#define VDEC2_ANC25_CANVAS_ADDR                    0x09a9
#define VDEC2_ANC26_CANVAS_ADDR                    0x09aa
#define VDEC2_ANC27_CANVAS_ADDR                    0x09ab
#define VDEC2_ANC28_CANVAS_ADDR                    0x09ac
#define VDEC2_ANC29_CANVAS_ADDR                    0x09ad
#define VDEC2_ANC30_CANVAS_ADDR                    0x09ae
#define VDEC2_ANC31_CANVAS_ADDR                    0x09af
#define VDEC2_DBKR_CANVAS_ADDR                     0x09b0
#define VDEC2_DBKW_CANVAS_ADDR                     0x09b1
#define VDEC2_REC_CANVAS_ADDR                      0x09b2
//28:24, read/write, current canvas idx, used in h264 only now
//23:0, read only, current canvas address, 23:16, Cr canvas addr, 15:8, Cb canvas addr, 7:0, Y  canvas addr
#define VDEC2_CURR_CANVAS_CTRL                     0x09b3
#define VDEC2_MDEC_PIC_DC_THRESH                   0x09b8
#define VDEC2_MDEC_PICR_BUF_STATUS                 0x09b9
#define VDEC2_MDEC_PICW_BUF_STATUS                 0x09ba
#define VDEC2_MCW_DBLK_WRRSP_CNT                   0x09bb
#define VDEC2_MC_MBBOT_WRRSP_CNT                   0x09bc
#define VDEC2_MDEC_PICW_BUF2_STATUS                0x09bd
#define VDEC2_WRRSP_FIFO_PICW_DBK                  0x09be
#define VDEC2_WRRSP_FIFO_PICW_MC                   0x09bf
#define VDEC2_AV_SCRATCH_0                         0x09c0
#define VDEC2_AV_SCRATCH_1                         0x09c1
#define VDEC2_AV_SCRATCH_2                         0x09c2
#define VDEC2_AV_SCRATCH_3                         0x09c3
#define VDEC2_AV_SCRATCH_4                         0x09c4
#define VDEC2_AV_SCRATCH_5                         0x09c5
#define VDEC2_AV_SCRATCH_6                         0x09c6
#define VDEC2_AV_SCRATCH_7                         0x09c7
#define VDEC2_AV_SCRATCH_8                         0x09c8
#define VDEC2_AV_SCRATCH_9                         0x09c9
#define VDEC2_AV_SCRATCH_A                         0x09ca
#define VDEC2_AV_SCRATCH_B                         0x09cb
#define VDEC2_AV_SCRATCH_C                         0x09cc
#define VDEC2_AV_SCRATCH_D                         0x09cd
#define VDEC2_AV_SCRATCH_E                         0x09ce
#define VDEC2_AV_SCRATCH_F                         0x09cf
#define VDEC2_AV_SCRATCH_G                         0x09d0
#define VDEC2_AV_SCRATCH_H                         0x09d1
#define VDEC2_AV_SCRATCH_I                         0x09d2
#define VDEC2_AV_SCRATCH_J                         0x09d3
#define VDEC2_AV_SCRATCH_K                         0x09d4
#define VDEC2_AV_SCRATCH_L                         0x09d5
#define VDEC2_AV_SCRATCH_M                         0x09d6
#define VDEC2_AV_SCRATCH_N                         0x09d7
// bit[29:24] A_brst_num_co_mb
// bit[21:16] A_id_co_mb
// bit[11:0] wrrsp_count_co_mb
#define VDEC2_WRRSP_CO_MB                          0x09d8
// bit[29:24] A_brst_num_dcac
// bit[21:16] A_id_dcac
// bit[11:0] wrrsp_count_dcac
#define VDEC2_WRRSP_DCAC                           0x09d9
//======================================
//  MC Control Register Bits
//
//======================================
// For bits, just copy the defines...don't translate to addresses
    //`define MC_RESET	    16'h0002
//======================================
//  MB Info Register Bits
//
//======================================
//======================================
//  MB Info Register Bits
//
//======================================
//========================================================================
// DBLK Register:  12'h950 - 12'h97f 
//========================================================================
#define VDEC2_DBLK_RST                             0x0950
#define VDEC2_DBLK_CTRL                            0x0951
#define VDEC2_DBLK_MB_WID_HEIGHT                   0x0952
#define VDEC2_DBLK_STATUS                          0x0953
#define VDEC2_DBLK_CMD_CTRL                        0x0954
#define VDEC2_DBLK_MB_XY                           0x0955
#define VDEC2_DBLK_QP                              0x0956
#define VDEC2_DBLK_Y_BHFILT                        0x0957
#define VDEC2_DBLK_Y_BHFILT_HIGH                   0x0958
#define VDEC2_DBLK_Y_BVFILT                        0x0959
#define VDEC2_DBLK_CB_BFILT                        0x095a
#define VDEC2_DBLK_CR_BFILT                        0x095b
#define VDEC2_DBLK_Y_HFILT                         0x095c
#define VDEC2_DBLK_Y_HFILT_HIGH                    0x095d
#define VDEC2_DBLK_Y_VFILT                         0x095e
#define VDEC2_DBLK_CB_FILT                         0x095f
#define VDEC2_DBLK_CR_FILT                         0x0960
#define VDEC2_DBLK_BETAX_QP_SEL                    0x0961
#define VDEC2_DBLK_CLIP_CTRL0                      0x0962
#define VDEC2_DBLK_CLIP_CTRL1                      0x0963
#define VDEC2_DBLK_CLIP_CTRL2                      0x0964
#define VDEC2_DBLK_CLIP_CTRL3                      0x0965
#define VDEC2_DBLK_CLIP_CTRL4                      0x0966
#define VDEC2_DBLK_CLIP_CTRL5                      0x0967
#define VDEC2_DBLK_CLIP_CTRL6                      0x0968
#define VDEC2_DBLK_CLIP_CTRL7                      0x0969
#define VDEC2_DBLK_CLIP_CTRL8                      0x096a
#define VDEC2_DBLK_STATUS1                         0x096b
#define VDEC2_DBLK_GCLK_FREE                       0x096c
#define VDEC2_DBLK_GCLK_OFF                        0x096d
#define VDEC2_DBLK_AVSFLAGS                        0x096e
// bit 15:0
#define VDEC2_DBLK_CBPY                            0x0970
// bit 11:8 -- deblk_cbpy_bottom
// bit 7:4 -- deblk_cbpy_left
// bit 3:0 -- deblk_cbpy_top
#define VDEC2_DBLK_CBPY_ADJ                        0x0971
// bit 7:0 -- deblk_cbpc
#define VDEC2_DBLK_CBPC                            0x0972
// bit 15 -- bottom_mb
// bit 14 -- left_mb
// bit 13 -- top_mb
// bit 12 -- reserved
// bit 11:8 -- deblk_cbpc_bottom
// bit 7:4 -- deblk_cbpc_left
// bit 3:0 -- deblk_cbpc_top
#define VDEC2_DBLK_CBPC_ADJ                        0x0973
// bit 15:8 -- deblk_hmvd   -- {left_1, left_0, below_1, below_0, block3-0} 
// bit 7:0 -- deblk_vmvd    -- {top_1, top_0, below_1, below_0, block3-0} 
#define VDEC2_DBLK_VHMVD                           0x0974
// bit 13:12 -- right_vmvd
// bit 11 -- right_above_vmvd
// bit 10 -- left_below_hmvd
// bit 9 -- disable_dblk_luma  
// bit 8 -- disable_dblk_chroma
// bit 7 -- bBelowRefDiff
// bit 6 -- bLeftRefDiff
// bit 5 -- bAboveRefDiff
// bit 4 -- reserved
// bit 3 -- s_below
// bit 2 -- s_left
// bit 1 -- s_above
// bit 0 -- s 
#define VDEC2_DBLK_STRONG                          0x0975
// bit 14:10 -- PQUANT 
// bit 9:5 -- left_PQUANT 
// bit 4:0 -- top_PQUANT 
#define VDEC2_DBLK_RV8_QUANT                       0x0976
#define VDEC2_DBLK_CBUS_HCMD2                      0x0977
#define VDEC2_DBLK_CBUS_HCMD1                      0x0978
#define VDEC2_DBLK_CBUS_HCMD0                      0x0979
#define VDEC2_DBLK_VLD_HCMD2                       0x097a
#define VDEC2_DBLK_VLD_HCMD1                       0x097b
#define VDEC2_DBLK_VLD_HCMD0                       0x097c
#define VDEC2_DBLK_OST_YBASE                       0x097d
#define VDEC2_DBLK_OST_CBCRDIFF                    0x097e
//13:8 dblk thread ID and token 
//5:0  dblk prearbitor burst num
#define VDEC2_DBLK_CTRL1                           0x097f
// MCRCC_CTL1
// 31:3  <reserved[23:0]>
// 2     <cfg_field_pic>
// 1     <sw_rst>
// 0     <bypass_en>
#define VDEC2_MCRCC_CTL1                           0x0980
// MCRCC_CTL2
// 31:24    <cfg_cache_anc01_c[7:0]>
// 23:16    <cfg_cache_anc01_y[7:0]>
// 15:8     <cfg_cache_anc00_c[7:0]>
// 7:0      <cfg_cache_anc00_y[7:0]>
#define VDEC2_MCRCC_CTL2                           0x0981
// MCRCC_CTL3
// 31:24    <cfg_cache_anc11_c[7:0]>
// 23:16    <cfg_cache_anc11_y[7:0]>
// 15:8     <cfg_cache_anc10_c[7:0]>
// 7:0      <cfg_cache_anc10_y[7:0]>
#define VDEC2_MCRCC_CTL3                           0x0982
// bit[31:10] reserved
// bit[9:0] sw_clock_gating control 
// [9] vdec clk_en for assist and cbus.
// [8] vdec clk_en for ddr
// [7] vdec clk_en for vcpu
// [6] vdec clk_en for assist
// [5] vdec clk_en for dblk
// [4] vdec clk_en for iqidct
// [3] vdec clk_en for mc
// [2] vdec clk_en for pic_dc
// [1] vdec clk_en for psc
// [0] vdec clk_en for vld
#define VDEC2_GCLK_EN                              0x0983
// [0]  Reserved 
// [1]  Reserved
// [2]  Reset assist, mdec's CBUS
// [3]  Reset mdec's VLD
// [4]  Reset mdec's VLD
// [5]  Reset mdec's VLD
// [6]  Reset mdec's IQIDCT
// [7]  Reset mdec's MC
// [8]  Reset mdec's DBLK
// [9]  Reset mdec's PIC_DC
// [10] Reset mdec's Pscale
// [11] Reset vcpu's MCPU
// [12] Reset vcpu's CCPU
// [13] Reset mmc_pre_arb
#define VDEC2_MDEC_SW_RESET                        0x0984
//DBLK last address 12'h97f
//
// Closing file:  mdec_regs.h
//
//
// Reading file:  vld_regs.h
//
//========================================================================
//  VLD module level register offset
//========================================================================
// -----------------------------------------------
// CBUS_BASE:  DOS_VDEC_VLD_CBUS_BASE = 0x0c
// -----------------------------------------------
#define HCODEC_VLD_STATUS_CTRL                     0x0c00
//
// bit 10 -- use_old_shift_en
// bit 9 -- output_mv_not_pmv
// bit 8:5 -- force_zigzag
// bit 4 -- force_zigzag_en
// bit 3 -- disable_viff_anempty_int
// bit 2 -- disable_m2_ac_coeff_one_cycle
// bit 1 -- forced_reset  force reset pmv
// bit 0 -- mpeg_type  0:mpeg1 1: mpeg2
#define HCODEC_MPEG1_2_REG                         0x0c01
#define HCODEC_F_CODE_REG                          0x0c02
#define HCODEC_PIC_HEAD_INFO                       0x0c03
#define HCODEC_SLICE_VER_POS_PIC_TYPE              0x0c04
#define HCODEC_QP_VALUE_REG                        0x0c05
#define HCODEC_MBA_INC                             0x0c06
#define HCODEC_MB_MOTION_MODE                      0x0c07
//`define PACKET_BYTE_COUNT   8'h08
// bit 15 -- force_search_startcode_en
// bit 14 -- int_cpu_when_error (before do anything)
// bit 13 -- vld_error_reset
// bit 12 -- return_on_slice_header
// bit 6 -- jpeg_ff00_en 
// bit 5:0 -- vld_power_ctl
#define HCODEC_POWER_CTL_VLD                       0x0c08
#define HCODEC_MB_WIDTH                            0x0c09
#define HCODEC_SLICE_QP                            0x0c0a
// `define MB_X_MB_Y           8'h0b   /* current MBX and MBY                  */
#define HCODEC_PRE_START_CODE                      0x0c0b
#define HCODEC_SLICE_START_BYTE_01                 0x0c0c
#define HCODEC_SLICE_START_BYTE_23                 0x0c0d
#define HCODEC_RESYNC_MARKER_LENGTH                0x0c0e
// bit[6:5] - frame/field info, 01 - top, 10 - bottom, 11 - frame
// bit[4:0] - buffer ID
// L0_BUFF_ID_0, L0_BUFF_ID_1, L1_BUFF_ID_0, L1_BUFF_ID_1
#define HCODEC_DECODER_BUFFER_INFO                 0x0c0f
#define HCODEC_FST_FOR_MV_X                        0x0c10
#define HCODEC_FST_FOR_MV_Y                        0x0c11
#define HCODEC_SCD_FOR_MV_X                        0x0c12
#define HCODEC_SCD_FOR_MV_Y                        0x0c13
#define HCODEC_FST_BAK_MV_X                        0x0c14
#define HCODEC_FST_BAK_MV_Y                        0x0c15
#define HCODEC_SCD_BAK_MV_X                        0x0c16
#define HCODEC_SCD_BAK_MV_Y                        0x0c17
// Bit 7:4 -- read_buffer_interlace  0-progressive, 1-interlace, used in VC1
// bit 3 -- reserved
// bit 2 -- weighting_prediction
// bit 1 -- mb_weighting_flag
// bit 0 -- slice_weighting_flag 
#define HCODEC_VLD_DECODE_CONTROL                  0x0c18
#define HCODEC_VLD_REVERVED_19                     0x0c19
#define HCODEC_VIFF_BIT_CNT                        0x0c1a
#define HCODEC_BYTE_ALIGN_PEAK_HI                  0x0c1b
#define HCODEC_BYTE_ALIGN_PEAK_LO                  0x0c1c
#define HCODEC_NEXT_ALIGN_PEAK                     0x0c1d
// bit 19    : vc1_inv_intra_co_mb_ref_rd
// bit 18    : vc1_inv_co_mb_ref_rd
// bit 17    : vc1_inv_intra_co_mb_ref_wr
// bit 16    : vc1_inv_co_mb_ref_wr
// bit 15    : reserved
// bit 14    : avs_drop_enable
// bit 13:12 : avs_drop_ptr
// bit 11:8  : avs_demu_ctl_reg
// bit 7 : avs_enable
// bit 6 : disable_dblk_hcmd
// bit 5 : disable_mc_hcmd
// bit 4 : first_mode3_set enable
// bit 3 : first_mode3
// bit 2:1 : vc1_profile  0-SP, 1-MP, 2-reserved, 3-AP
// bit 0   : vc1_enable
#define HCODEC_VC1_CONTROL_REG                     0x0c1e
#define HCODEC_PMV1_X                              0x0c20
#define HCODEC_PMV1_Y                              0x0c21
#define HCODEC_PMV2_X                              0x0c22
#define HCODEC_PMV2_Y                              0x0c23
#define HCODEC_PMV3_X                              0x0c24
#define HCODEC_PMV3_Y                              0x0c25
#define HCODEC_PMV4_X                              0x0c26
#define HCODEC_PMV4_Y                              0x0c27
// Can't use the same address for different defines
// Therefore, create a single define that covers both
// Only appears to be used in micro-code since the VLD hardware is 
// hard coded.
// `define M4_TABLE_SELECT     8'h28  // Does this exist in HW ? Added from register_mp2.h
// `define M4_TABLE_OUTPUT     8'h28  // Does this exist in HW ? Added from register_mp2.h
#define HCODEC_M4_TABLE_SELECT                     0x0c28
#define HCODEC_M4_CONTROL_REG                      0x0c29
#define HCODEC_BLOCK_NUM                           0x0c2a
#define HCODEC_PATTERN_CODE                        0x0c2b
#define HCODEC_MB_INFO                             0x0c2c
#define HCODEC_VLD_DC_PRED                         0x0c2d
#define HCODEC_VLD_ERROR_MASK                      0x0c2e
#define HCODEC_VLD_DC_PRED_C                       0x0c2f
#define HCODEC_LAST_SLICE_MV_ADDR                  0x0c30
#define HCODEC_LAST_MVX                            0x0c31
#define HCODEC_LAST_MVY                            0x0c32
#define HCODEC_VLD_C38                             0x0c38
#define HCODEC_VLD_C39                             0x0c39
#define HCODEC_VLD_STATUS                          0x0c3a
#define HCODEC_VLD_SHIFT_STATUS                    0x0c3b
// `define VLD_SHIFT_INFO      8'h3b  // Does this exist in HW ? used in $ucode/mpeg4
#define HCODEC_VOFF_STATUS                         0x0c3c
#define HCODEC_VLD_C3D                             0x0c3d
#define HCODEC_VLD_DBG_INDEX                       0x0c3e
// vld_buff_info -- (index == 0) 
// Bit[7:6]  mv_UR_ready_cnt;
// Bit[5]  vld_wr_idx
// Bit[4]  iq_rd_idx
// Bit[3]  vld_vi_block_rdy_1
// Bit[2]  vld_vi_block_rdy_2
// Bit[1]  voff_empty_1
// Bit[0]  voff_empty_2
// cabac_buff_info_0 -- (index == 1) 
// Bit[31] shift_data_ready
// Bit[30:29] Reserved
// Bit[28:24] cabac_buffer_ptr
// Bit[23:0] cabac_buffer
// cabac_buff_info_1 -- (index == 2) 
// Bit[31:29] Reserved
// Bit[28:20] Drange
// Bit[19:16] bin_count_4
// Bit[15:13] Reserved
// Bit[12:6] context_mem_do
// Bit[5:3] coeff_state
// Bit[2:0] mvd_state
// h264_mv_present -- (index == 3) 
// Bit[31:16] mv_present_l0
// Bit[15:0] mv_present_l1
// h264_mv_cal_info_0 -- (index == 4) 
// [31:28] mv_cal_state
// [27:24] direct_spatial_cnt
// Bit[23:21] Reserved
// Bit[20] mv_UR_ready_for_mv_cal
// Bit[19] co_mb_mem_ready_for_mv_cal
// Bit[18] mc_dblk_cmd_if_busy
// Bit[17] h264_co_mb_wr_busy
// Bit[16] H264_cbp_blk_ready
// Bit[15] mc_hcmd_rrdy
// Bit[14] mc_hcmd_srdy
// Bit[13] mc_cmd_if_ready
// Bit[12] mc_hcmd_mv_available
// Bit[11:8] mc_cmd_if_state
// Bit[7] dblk_hcmd_rrdy
// Bit[6] dblk_hcmd_srdy
// Bit[5] dblk_cmd_if_ready
// Bit[4] dblk_hcmd_mv_available
// Bit[3:0] dblk_cmd_if_state
// h264_mv_cal_info_1 -- (index == 5) 
//  Bit[31:29] Reserved
//  Bit[28:24] total_mvd_num_l0
//  Bit[23:21] Reserved
//  Bit[20:16] mv_cal_ptr_l0
//  Bit[15:13] Reserved
//  Bit[12:8] mc_hcmd_ptr_l0
//  Bit[7:5] Reserved
//  Bit[4:0] dblk_hcmd_ptr_l0
// h264_mv_cal_info_2 -- (index == 6) 
//  Bit[31:29] Reserved
//  Bit[28:24] total_mvd_num_l1
//  Bit[23:21] Reserved
//  Bit[20:16] mv_cal_ptr_l1
//  Bit[15:13] Reserved
//  Bit[12:8] mc_hcmd_ptr_l1
//  Bit[7:5] Reserved
//  Bit[4:0] dblk_hcmd_ptr_l1
// h264_co_mb_info -- (index == 7)
// Bit[31:26] Reserved
// Bit[25] mv_scale_cal_busy
// Bit[24:20] co_mv_count
// Bit[19:16] co_mv_process_state
// Bit[15] h264_co_mb_rd_busy
// Bit[15] h264_co_mb_rd_ready
// Bit[13:12] co_mv_transfer_block_cnt
// Bit[11:8] co_mv_transfer_ptr
// Bit[7] co_mv_POC_l1_busy
// Bit[6] h264_weight_scale_cal_en
// Bit[5] weight_cal_busy
// Bit[4] weight_cal_not_finished
// Bit[3:0] weight_process_state
#define HCODEC_VLD_DBG_DATA                        0x0c3f
// --------------------------------------------
// VIFIFO DDR Interface
// --------------------------------------------
// The VIFIFO start pointer into DDR memory is a 32-bit number
// The Start pointer will automatically be truncated to land on 
// an 8-byte boundary.  That is, bits [2:0] = 0;
#define HCODEC_VLD_MEM_VIFIFO_START_PTR            0x0c40
// The current pointer points so some location between the START and END 
// pointers.  The current pointer is a BYTE pointer.  That is, you can 
// point to any BYTE address within the START/END range
#define HCODEC_VLD_MEM_VIFIFO_CURR_PTR             0x0c41
#define HCODEC_VLD_MEM_VIFIFO_END_PTR              0x0c42
#define HCODEC_VLD_MEM_VIFIFO_BYTES_AVAIL          0x0c43
// VIFIFO FIFO Control
// bit  [31:24] viff_empty_int_enable_cpu[7:0] 
// bit  [23:16] viff_empty_int_enable_amrisc[7:0] 
//   -bit 23 Video BUFFER < 0x400 Bytes
//   -bit 22 Video BUFFER < 0x200 Bytes
//   -bit 21 Video BUFFER < 0x100 Bytes
//   -bit 20 Video BUFFER < 0x80 Bytes
//   -bit 19 Video BUFFER < 0x40 Bytes
//   -bit 18 Video BUFFER < 0x20 Bytes
//   -bit 17 vififo  < 16 double words
//   -bit 16 vififo  < 8 double words
// bit  [15:13] unused
// bit  [12]    A_urgent
// bit  [11]    transfer_length 0 - 32x64 Bits per request, 1 - 16x64 Bits per request
// bit  [10]    use_level       Set this bit to 1 to enable filling of the FIFO controlled by the buffer
//                              level control.  If this bit is 0, then use bit[1] to control the enabling of filling
// bit  [9]     Data Ready.     This bit is set when data can be popped
// bit  [8]     fill busy       This bit will be high when we're fetching data from the DDR memory
//                              To reset this module, set cntl_enable = 0, and then wait for busy = 0. 
//                              After that you can pulse cntl_init to start over
// bit  [7]     init_with_cntl_init
// bit  [6]     reserved
// bits [5:3]   endian:         see $lib/rtl/ddr_endian.v
// bit  [2]     cntl_empty_en   Set to 1 to enable reading the DDR memory FIFO
//                              Set cntl_empty_en = cntl_fill_en = 0 when pulsing cntl_init
// bit  [1]     cntl_fill_en    Set to 1 to enable reading data from DDR memory
// bit  [0]     cntl_init:      After setting the read pointers, sizes, channel masks
//                              and read masks, set this bit to 1 and then to 0
//                              NOTE:  You don't need to pulse cntl_init if only the start address is
//                              being changed
#define HCODEC_VLD_MEM_VIFIFO_CONTROL              0x0c44
// --------------------------------------------
// VIFIFO Buffer Level Manager
// --------------------------------------------
#define HCODEC_VLD_MEM_VIFIFO_WP                   0x0c45
#define HCODEC_VLD_MEM_VIFIFO_RP                   0x0c46
#define HCODEC_VLD_MEM_VIFIFO_LEVEL                0x0c47
//
// bit  [8]     use_parser_video2_wp
// bit  [7]     vbuf2_out_manual
// bit  [6]     vbuf_out_manual
// bit  [5]     empty (ReadOnly)
// bit  [4]     full (ReadOnly)
// bit  [3:2]   reserved
// bit  [1]     manual mode     Set to 1 for manual write pointer mode
// bit  [0]     Init            Set high then low after everything has been initialized
#define HCODEC_VLD_MEM_VIFIFO_BUF_CNTL             0x0c48
// bit 31:16 -- drop_bytes
// bit 15:14 -- drop_status (Read-Only)
// bit 13:12 -- sync_match_position (Read-Only)
// bit 11:6 -- reserved
// bit 5:4 -- TIME_STAMP_NUMBER, 0-32bits, 1-64bits, 2-96bits, 3-128bits 
// bit 3 -- stamp_soft_reset
// bit 2 -- TIME_STAMP_length_enable
// bit 1 -- TIME_STAMP_sync64_enable
// bit 0 -- TIME_STAMP_enable
#define HCODEC_VLD_TIME_STAMP_CNTL                 0x0c49
// bit 31:0 -- TIME_STAMP_SYNC_CODE_0
#define HCODEC_VLD_TIME_STAMP_SYNC_0               0x0c4a
// bit 31:0 -- TIME_STAMP_SYNC_CODE_1 
#define HCODEC_VLD_TIME_STAMP_SYNC_1               0x0c4b
// bit 31:0 TIME_STAMP_0
#define HCODEC_VLD_TIME_STAMP_0                    0x0c4c
// bit 31:0 TIME_STAMP_1
#define HCODEC_VLD_TIME_STAMP_1                    0x0c4d
// bit 31:0 TIME_STAMP_2
#define HCODEC_VLD_TIME_STAMP_2                    0x0c4e
// bit 31:0 TIME_STAMP_3
#define HCODEC_VLD_TIME_STAMP_3                    0x0c4f
// bit 31:0 TIME_STAMP_LENGTH
#define HCODEC_VLD_TIME_STAMP_LENGTH               0x0c50
// bit 15:0 vififo_rd_count
#define HCODEC_VLD_MEM_VIFIFO_WRAP_COUNT           0x0c51
// bit 29:24 A_brst_num
// bit 21:16 A_id
// bit 15:0 level_hold 
#define HCODEC_VLD_MEM_VIFIFO_MEM_CTL              0x0c52
#define HCODEC_VLD_MEM_VBUF_RD_PTR                 0x0c53
#define HCODEC_VLD_MEM_VBUF2_RD_PTR                0x0c54
#define HCODEC_VLD_MEM_SWAP_ADDR                   0x0c55
// bit[23:16] - swap_d_count (Read Only)
// bit[15:8]  - swap_a_count (Read Only)
// bit [7] - swap busy (Read Only)
// bit [6:2] - reserved
// bit [1] - 1 - STORE to Memory, 0 - LOAD from Memory
// bit [0] - swap active
#define HCODEC_VLD_MEM_SWAP_CTL                    0x0c56
//
// Closing file:  vld_regs.h
//
//
// Reading file:  vld_regs.h
//
//========================================================================
//  VLD module level register offset
//========================================================================
// -----------------------------------------------
// CBUS_BASE:  DOS_VDEC_VLD_CBUS_BASE = 0x0c
// -----------------------------------------------
#define VDEC2_VLD_STATUS_CTRL                      0x0c00
//
// bit 10 -- use_old_shift_en
// bit 9 -- output_mv_not_pmv
// bit 8:5 -- force_zigzag
// bit 4 -- force_zigzag_en
// bit 3 -- disable_viff_anempty_int
// bit 2 -- disable_m2_ac_coeff_one_cycle
// bit 1 -- forced_reset  force reset pmv
// bit 0 -- mpeg_type  0:mpeg1 1: mpeg2
#define VDEC2_MPEG1_2_REG                          0x0c01
#define VDEC2_F_CODE_REG                           0x0c02
#define VDEC2_PIC_HEAD_INFO                        0x0c03
#define VDEC2_SLICE_VER_POS_PIC_TYPE               0x0c04
#define VDEC2_QP_VALUE_REG                         0x0c05
#define VDEC2_MBA_INC                              0x0c06
#define VDEC2_MB_MOTION_MODE                       0x0c07
//`define PACKET_BYTE_COUNT   8'h08
// bit 15 -- force_search_startcode_en
// bit 14 -- int_cpu_when_error (before do anything)
// bit 13 -- vld_error_reset
// bit 12 -- return_on_slice_header
// bit 6 -- jpeg_ff00_en 
// bit 5:0 -- vld_power_ctl
#define VDEC2_POWER_CTL_VLD                        0x0c08
#define VDEC2_MB_WIDTH                             0x0c09
#define VDEC2_SLICE_QP                             0x0c0a
// `define MB_X_MB_Y           8'h0b   /* current MBX and MBY                  */
#define VDEC2_PRE_START_CODE                       0x0c0b
#define VDEC2_SLICE_START_BYTE_01                  0x0c0c
#define VDEC2_SLICE_START_BYTE_23                  0x0c0d
#define VDEC2_RESYNC_MARKER_LENGTH                 0x0c0e
// bit[6:5] - frame/field info, 01 - top, 10 - bottom, 11 - frame
// bit[4:0] - buffer ID
// L0_BUFF_ID_0, L0_BUFF_ID_1, L1_BUFF_ID_0, L1_BUFF_ID_1
#define VDEC2_DECODER_BUFFER_INFO                  0x0c0f
#define VDEC2_FST_FOR_MV_X                         0x0c10
#define VDEC2_FST_FOR_MV_Y                         0x0c11
#define VDEC2_SCD_FOR_MV_X                         0x0c12
#define VDEC2_SCD_FOR_MV_Y                         0x0c13
#define VDEC2_FST_BAK_MV_X                         0x0c14
#define VDEC2_FST_BAK_MV_Y                         0x0c15
#define VDEC2_SCD_BAK_MV_X                         0x0c16
#define VDEC2_SCD_BAK_MV_Y                         0x0c17
// Bit 7:4 -- read_buffer_interlace  0-progressive, 1-interlace, used in VC1
// bit 3 -- reserved
// bit 2 -- weighting_prediction
// bit 1 -- mb_weighting_flag
// bit 0 -- slice_weighting_flag 
#define VDEC2_VLD_DECODE_CONTROL                   0x0c18
#define VDEC2_VLD_REVERVED_19                      0x0c19
#define VDEC2_VIFF_BIT_CNT                         0x0c1a
#define VDEC2_BYTE_ALIGN_PEAK_HI                   0x0c1b
#define VDEC2_BYTE_ALIGN_PEAK_LO                   0x0c1c
#define VDEC2_NEXT_ALIGN_PEAK                      0x0c1d
// bit 19    : vc1_inv_intra_co_mb_ref_rd
// bit 18    : vc1_inv_co_mb_ref_rd
// bit 17    : vc1_inv_intra_co_mb_ref_wr
// bit 16    : vc1_inv_co_mb_ref_wr
// bit 15    : reserved
// bit 14    : avs_drop_enable
// bit 13:12 : avs_drop_ptr
// bit 11:8  : avs_demu_ctl_reg
// bit 7 : avs_enable
// bit 6 : disable_dblk_hcmd
// bit 5 : disable_mc_hcmd
// bit 4 : first_mode3_set enable
// bit 3 : first_mode3
// bit 2:1 : vc1_profile  0-SP, 1-MP, 2-reserved, 3-AP
// bit 0   : vc1_enable
#define VDEC2_VC1_CONTROL_REG                      0x0c1e
#define VDEC2_PMV1_X                               0x0c20
#define VDEC2_PMV1_Y                               0x0c21
#define VDEC2_PMV2_X                               0x0c22
#define VDEC2_PMV2_Y                               0x0c23
#define VDEC2_PMV3_X                               0x0c24
#define VDEC2_PMV3_Y                               0x0c25
#define VDEC2_PMV4_X                               0x0c26
#define VDEC2_PMV4_Y                               0x0c27
// Can't use the same address for different defines
// Therefore, create a single define that covers both
// Only appears to be used in micro-code since the VLD hardware is 
// hard coded.
// `define M4_TABLE_SELECT     8'h28  // Does this exist in HW ? Added from register_mp2.h
// `define M4_TABLE_OUTPUT     8'h28  // Does this exist in HW ? Added from register_mp2.h
#define VDEC2_M4_TABLE_SELECT                      0x0c28
#define VDEC2_M4_CONTROL_REG                       0x0c29
#define VDEC2_BLOCK_NUM                            0x0c2a
#define VDEC2_PATTERN_CODE                         0x0c2b
#define VDEC2_MB_INFO                              0x0c2c
#define VDEC2_VLD_DC_PRED                          0x0c2d
#define VDEC2_VLD_ERROR_MASK                       0x0c2e
#define VDEC2_VLD_DC_PRED_C                        0x0c2f
#define VDEC2_LAST_SLICE_MV_ADDR                   0x0c30
#define VDEC2_LAST_MVX                             0x0c31
#define VDEC2_LAST_MVY                             0x0c32
#define VDEC2_VLD_C38                              0x0c38
#define VDEC2_VLD_C39                              0x0c39
#define VDEC2_VLD_STATUS                           0x0c3a
#define VDEC2_VLD_SHIFT_STATUS                     0x0c3b
// `define VLD_SHIFT_INFO      8'h3b  // Does this exist in HW ? used in $ucode/mpeg4
#define VDEC2_VOFF_STATUS                          0x0c3c
#define VDEC2_VLD_C3D                              0x0c3d
#define VDEC2_VLD_DBG_INDEX                        0x0c3e
// vld_buff_info -- (index == 0) 
// Bit[7:6]  mv_UR_ready_cnt;
// Bit[5]  vld_wr_idx
// Bit[4]  iq_rd_idx
// Bit[3]  vld_vi_block_rdy_1
// Bit[2]  vld_vi_block_rdy_2
// Bit[1]  voff_empty_1
// Bit[0]  voff_empty_2
// cabac_buff_info_0 -- (index == 1) 
// Bit[31] shift_data_ready
// Bit[30:29] Reserved
// Bit[28:24] cabac_buffer_ptr
// Bit[23:0] cabac_buffer
// cabac_buff_info_1 -- (index == 2) 
// Bit[31:29] Reserved
// Bit[28:20] Drange
// Bit[19:16] bin_count_4
// Bit[15:13] Reserved
// Bit[12:6] context_mem_do
// Bit[5:3] coeff_state
// Bit[2:0] mvd_state
// h264_mv_present -- (index == 3) 
// Bit[31:16] mv_present_l0
// Bit[15:0] mv_present_l1
// h264_mv_cal_info_0 -- (index == 4) 
// [31:28] mv_cal_state
// [27:24] direct_spatial_cnt
// Bit[23:21] Reserved
// Bit[20] mv_UR_ready_for_mv_cal
// Bit[19] co_mb_mem_ready_for_mv_cal
// Bit[18] mc_dblk_cmd_if_busy
// Bit[17] h264_co_mb_wr_busy
// Bit[16] H264_cbp_blk_ready
// Bit[15] mc_hcmd_rrdy
// Bit[14] mc_hcmd_srdy
// Bit[13] mc_cmd_if_ready
// Bit[12] mc_hcmd_mv_available
// Bit[11:8] mc_cmd_if_state
// Bit[7] dblk_hcmd_rrdy
// Bit[6] dblk_hcmd_srdy
// Bit[5] dblk_cmd_if_ready
// Bit[4] dblk_hcmd_mv_available
// Bit[3:0] dblk_cmd_if_state
// h264_mv_cal_info_1 -- (index == 5) 
//  Bit[31:29] Reserved
//  Bit[28:24] total_mvd_num_l0
//  Bit[23:21] Reserved
//  Bit[20:16] mv_cal_ptr_l0
//  Bit[15:13] Reserved
//  Bit[12:8] mc_hcmd_ptr_l0
//  Bit[7:5] Reserved
//  Bit[4:0] dblk_hcmd_ptr_l0
// h264_mv_cal_info_2 -- (index == 6) 
//  Bit[31:29] Reserved
//  Bit[28:24] total_mvd_num_l1
//  Bit[23:21] Reserved
//  Bit[20:16] mv_cal_ptr_l1
//  Bit[15:13] Reserved
//  Bit[12:8] mc_hcmd_ptr_l1
//  Bit[7:5] Reserved
//  Bit[4:0] dblk_hcmd_ptr_l1
// h264_co_mb_info -- (index == 7)
// Bit[31:26] Reserved
// Bit[25] mv_scale_cal_busy
// Bit[24:20] co_mv_count
// Bit[19:16] co_mv_process_state
// Bit[15] h264_co_mb_rd_busy
// Bit[15] h264_co_mb_rd_ready
// Bit[13:12] co_mv_transfer_block_cnt
// Bit[11:8] co_mv_transfer_ptr
// Bit[7] co_mv_POC_l1_busy
// Bit[6] h264_weight_scale_cal_en
// Bit[5] weight_cal_busy
// Bit[4] weight_cal_not_finished
// Bit[3:0] weight_process_state
#define VDEC2_VLD_DBG_DATA                         0x0c3f
// --------------------------------------------
// VIFIFO DDR Interface
// --------------------------------------------
// The VIFIFO start pointer into DDR memory is a 32-bit number
// The Start pointer will automatically be truncated to land on 
// an 8-byte boundary.  That is, bits [2:0] = 0;
#define VDEC2_VLD_MEM_VIFIFO_START_PTR             0x0c40
// The current pointer points so some location between the START and END 
// pointers.  The current pointer is a BYTE pointer.  That is, you can 
// point to any BYTE address within the START/END range
#define VDEC2_VLD_MEM_VIFIFO_CURR_PTR              0x0c41
#define VDEC2_VLD_MEM_VIFIFO_END_PTR               0x0c42
#define VDEC2_VLD_MEM_VIFIFO_BYTES_AVAIL           0x0c43
// VIFIFO FIFO Control
// bit  [31:24] viff_empty_int_enable_cpu[7:0] 
// bit  [23:16] viff_empty_int_enable_amrisc[7:0] 
//   -bit 23 Video BUFFER < 0x400 Bytes
//   -bit 22 Video BUFFER < 0x200 Bytes
//   -bit 21 Video BUFFER < 0x100 Bytes
//   -bit 20 Video BUFFER < 0x80 Bytes
//   -bit 19 Video BUFFER < 0x40 Bytes
//   -bit 18 Video BUFFER < 0x20 Bytes
//   -bit 17 vififo  < 16 double words
//   -bit 16 vififo  < 8 double words
// bit  [15:13] unused
// bit  [12]    A_urgent
// bit  [11]    transfer_length 0 - 32x64 Bits per request, 1 - 16x64 Bits per request
// bit  [10]    use_level       Set this bit to 1 to enable filling of the FIFO controlled by the buffer
//                              level control.  If this bit is 0, then use bit[1] to control the enabling of filling
// bit  [9]     Data Ready.     This bit is set when data can be popped
// bit  [8]     fill busy       This bit will be high when we're fetching data from the DDR memory
//                              To reset this module, set cntl_enable = 0, and then wait for busy = 0. 
//                              After that you can pulse cntl_init to start over
// bit  [7]     init_with_cntl_init
// bit  [6]     reserved
// bits [5:3]   endian:         see $lib/rtl/ddr_endian.v
// bit  [2]     cntl_empty_en   Set to 1 to enable reading the DDR memory FIFO
//                              Set cntl_empty_en = cntl_fill_en = 0 when pulsing cntl_init
// bit  [1]     cntl_fill_en    Set to 1 to enable reading data from DDR memory
// bit  [0]     cntl_init:      After setting the read pointers, sizes, channel masks
//                              and read masks, set this bit to 1 and then to 0
//                              NOTE:  You don't need to pulse cntl_init if only the start address is
//                              being changed
#define VDEC2_VLD_MEM_VIFIFO_CONTROL               0x0c44
// --------------------------------------------
// VIFIFO Buffer Level Manager
// --------------------------------------------
#define VDEC2_VLD_MEM_VIFIFO_WP                    0x0c45
#define VDEC2_VLD_MEM_VIFIFO_RP                    0x0c46
#define VDEC2_VLD_MEM_VIFIFO_LEVEL                 0x0c47
//
// bit  [8]     use_parser_video2_wp
// bit  [7]     vbuf2_out_manual
// bit  [6]     vbuf_out_manual
// bit  [5]     empty (ReadOnly)
// bit  [4]     full (ReadOnly)
// bit  [3:2]   reserved
// bit  [1]     manual mode     Set to 1 for manual write pointer mode
// bit  [0]     Init            Set high then low after everything has been initialized
#define VDEC2_VLD_MEM_VIFIFO_BUF_CNTL              0x0c48
// bit 31:16 -- drop_bytes
// bit 15:14 -- drop_status (Read-Only)
// bit 13:12 -- sync_match_position (Read-Only)
// bit 11:6 -- reserved
// bit 5:4 -- TIME_STAMP_NUMBER, 0-32bits, 1-64bits, 2-96bits, 3-128bits 
// bit 3 -- stamp_soft_reset
// bit 2 -- TIME_STAMP_length_enable
// bit 1 -- TIME_STAMP_sync64_enable
// bit 0 -- TIME_STAMP_enable
#define VDEC2_VLD_TIME_STAMP_CNTL                  0x0c49
// bit 31:0 -- TIME_STAMP_SYNC_CODE_0
#define VDEC2_VLD_TIME_STAMP_SYNC_0                0x0c4a
// bit 31:0 -- TIME_STAMP_SYNC_CODE_1 
#define VDEC2_VLD_TIME_STAMP_SYNC_1                0x0c4b
// bit 31:0 TIME_STAMP_0
#define VDEC2_VLD_TIME_STAMP_0                     0x0c4c
// bit 31:0 TIME_STAMP_1
#define VDEC2_VLD_TIME_STAMP_1                     0x0c4d
// bit 31:0 TIME_STAMP_2
#define VDEC2_VLD_TIME_STAMP_2                     0x0c4e
// bit 31:0 TIME_STAMP_3
#define VDEC2_VLD_TIME_STAMP_3                     0x0c4f
// bit 31:0 TIME_STAMP_LENGTH
#define VDEC2_VLD_TIME_STAMP_LENGTH                0x0c50
// bit 15:0 vififo_rd_count
#define VDEC2_VLD_MEM_VIFIFO_WRAP_COUNT            0x0c51
// bit 29:24 A_brst_num
// bit 21:16 A_id
// bit 15:0 level_hold 
#define VDEC2_VLD_MEM_VIFIFO_MEM_CTL               0x0c52
#define VDEC2_VLD_MEM_VBUF_RD_PTR                  0x0c53
#define VDEC2_VLD_MEM_VBUF2_RD_PTR                 0x0c54
#define VDEC2_VLD_MEM_SWAP_ADDR                    0x0c55
// bit[23:16] - swap_d_count (Read Only)
// bit[15:8]  - swap_a_count (Read Only)
// bit [7] - swap busy (Read Only)
// bit [6:2] - reserved
// bit [1] - 1 - STORE to Memory, 0 - LOAD from Memory
// bit [0] - swap active
#define VDEC2_VLD_MEM_SWAP_CTL                     0x0c56
//
// Closing file:  vld_regs.h
//
//
// Reading file:  iqidct_regs.h
//
//========================================================================
//  IQ/IDCT module level register offset
//========================================================================
// -----------------------------------------------
// CBUS_BASE:  DOS_VDEC_IQIDCT_CBUS_BASE = 0x0e
// -----------------------------------------------
#define HCODEC_VCOP_CTRL_REG                       0x0e00
#define HCODEC_QP_CTRL_REG                         0x0e01
#define HCODEC_INTRA_QUANT_MATRIX                  0x0e02
#define HCODEC_NON_I_QUANT_MATRIX                  0x0e03
#define HCODEC_DC_SCALER                           0x0e04
#define HCODEC_DC_AC_CTRL                          0x0e05
// `define RV_AI_CTRL          8'h05  // ONLY for $ucode/real/amrisc/rv.s reg value from apollo
#define HCODEC_DC_AC_SCALE_MUL                     0x0e06
#define HCODEC_DC_AC_SCALE_DIV                     0x0e07
// `define DC_AC_SCALE_RESULT  8'h06
// `define RESERVED_E07        8'h07
#define HCODEC_POWER_CTL_IQIDCT                    0x0e08
#define HCODEC_RV_AI_Y_X                           0x0e09
#define HCODEC_RV_AI_U_X                           0x0e0a
#define HCODEC_RV_AI_V_X                           0x0e0b
// bit 15:0 will count up when rv_ai_mb finished when non zero
// and rv_ai_mb_finished_int will be generate when this is not zero
#define HCODEC_RV_AI_MB_COUNT                      0x0e0c
// For H264 I in PB picture Use -- dma type : h264_next_intra_dma
#define HCODEC_NEXT_INTRA_DMA_ADDRESS              0x0e0d
// Bit 0 -- constrained_intra_pred_flag for H264
#define HCODEC_IQIDCT_CONTROL                      0x0e0e
// Bit[31:19] Reserved
// Bit[18] iq_waiting
// Bit[17] iq_om_wr_idx
// Bit[16] iq_om_rd_idx
// Bit[15] iq_om_busy
// Bit[14] iq_om_2_busy 
// Bit[13] idx_fifo_0
// Bit[12] idx_fifo_1
// Bit[11] idx_fifo_2
// Bit[10] idx_fifo_3
// Bit[9] idx_fifo_4
// Bit[8] idx_fifo_5
// Bit[7] idx_fifo_6
// Bit[6] idx_fifo_7
// Bit[5:3] idx_fifo_wp
// Bit[2:0] idx_fifo_rp
#define HCODEC_IQIDCT_DEBUG_INFO_0                 0x0e0f
// For RTL Simulation Only
#define HCODEC_DEBLK_CMD                           0x0e10
// Bit[15+16] ds_mc_valid_2
// Bit[14+16] new_idct1_rd_idx_2
// Bit[13+16] new_idct1_wr_idx_2
// Bit[12+16] idct1_buff0_busy_2
// Bit[11+16] idct1_buff1_busy_2
// Bit[10+16] new_idct1_busy_2
// Bit[9+16] iq_om_8val_2
// Bit[8+16] idct1_pipe_busy_2
// Bit[7+16] wait_mb_left_finish_hold_2
// Bit[6+16] new_idct2_rd_idx_2
// Bit[5+16] new_idct2_wr_idx_2
// Bit[4+16] idct2_buff0_busy_2
// Bit[3+16] idct2_buff1_busy_2
// Bit[2+16] idct2_en_2
// Bit[1+16] new_idct2_busy_2
// Bit[0+16] new_idct1_ready_2
// Bit[15] ds_mc_valid_1
// Bit[14] new_idct1_rd_idx_1
// Bit[13] new_idct1_wr_idx_1
// Bit[12] idct1_buff0_busy_1
// Bit[11] idct1_buff1_busy_1
// Bit[10] new_idct1_busy_1
// Bit[9] iq_om_8val_1
// Bit[8] idct1_pipe_busy_1
// Bit[7] wait_mb_left_finish_hold_1
// Bit[6] new_idct2_rd_idx_1
// Bit[5] new_idct2_wr_idx_1
// Bit[4] idct2_buff0_busy_1
// Bit[3] idct2_buff1_busy_1
// Bit[2] idct2_en_1
// Bit[1] new_idct2_busy_1
// Bit[0] new_idct1_ready_1
#define HCODEC_IQIDCT_DEBUG_IDCT                   0x0e11
// bit 31 -- convas_enable
// bit 30:24 -- convas_x_count ( 8 pixels / 64 bits )
// bit 23:16 -- convas_y_count
// bit 15   -- dcac_dma_busy
// bit 14   -- dcac_dma_urgent
// bit 13:8 -- dcac_dma_count
// bit 7    -- dcac_dma_rw
// bit 6    -- dcac_skip_read_mode
// bit 5:0  -- dcac_dma_offset
#define HCODEC_DCAC_DMA_CTRL                       0x0e12
// when (convas_enable == 0 )
//   bit 31:0 dcac_dma_addr
// when (convas_enable == 1 )
//   bit 31:25 canvas_addr (7 bits)
//   bit 24:12 convas_y_start ( 13 btis )
//   bit 11:0  convas_x_start ( 12 btis )
#define HCODEC_DCAC_DMA_ADDRESS                    0x0e13
// bit 7:0 -- dcac_cpu_addr
#define HCODEC_DCAC_CPU_ADDRESS                    0x0e14
// bit 31:0 -- dcac_cpu_data
#define HCODEC_DCAC_CPU_DATA                       0x0e15
// bit 31:19 -- reserved
// bit 18:16 -- block_num_reg -- Read-Only 
// bit 15:0 -- dcac_mb_count
#define HCODEC_DCAC_MB_COUNT                       0x0e16
// bit 31:18 -- reserved
// For H264 :
//   bit 17:2 -- h264_quant 
//   bit 11:6 -- h264_quant_c 
//   bit  5:0 -- h264_quant_c 
// For VC1 :
//   bit    17 -- qindex_GT_8
//   bit    16 -- HalfQPStep
//   bit 15:12 -- eQuantMode 
//   bit 11:6  -- AltPQuant 
//   bit  5:0  -- PQuant 
//             
#define HCODEC_IQ_QUANT                            0x0e17
// bit 31:24  -- bitplane_width 
// bit 23:16  -- bitplane_height 
// bit 15:14  -- bitplane_start_x 
// bit 13:12  -- bitplane_start_y 
// bit 11:4   -- reserved
// bit 3:1    -- bitplane_type
// bit 0      -- bitplane_busy
#define HCODEC_VC1_BITPLANE_CTL                    0x0e18
//======================================
//  VCOP Control Register Bits
//
//======================================
    //`define IQIDCT_RESET	    16'h0001	    // Bit 0
//======================================
//  QP Control Register Bits
//
//======================================
// Duplicate Address:  When actually used
// please move to a different address
// `define FLD_DCT_TYPE	    16'h0100	    // Bit 8	0 = Frame DCT; 1 = field DCT
//
// Closing file:  iqidct_regs.h
//
//
// Reading file:  iqidct_regs.h
//
//========================================================================
//  IQ/IDCT module level register offset
//========================================================================
// -----------------------------------------------
// CBUS_BASE:  DOS_VDEC_IQIDCT_CBUS_BASE = 0x0e
// -----------------------------------------------
#define VDEC2_VCOP_CTRL_REG                        0x0e00
#define VDEC2_QP_CTRL_REG                          0x0e01
#define VDEC2_INTRA_QUANT_MATRIX                   0x0e02
#define VDEC2_NON_I_QUANT_MATRIX                   0x0e03
#define VDEC2_DC_SCALER                            0x0e04
#define VDEC2_DC_AC_CTRL                           0x0e05
// `define RV_AI_CTRL          8'h05  // ONLY for $ucode/real/amrisc/rv.s reg value from apollo
#define VDEC2_DC_AC_SCALE_MUL                      0x0e06
#define VDEC2_DC_AC_SCALE_DIV                      0x0e07
// `define DC_AC_SCALE_RESULT  8'h06
// `define RESERVED_E07        8'h07
#define VDEC2_POWER_CTL_IQIDCT                     0x0e08
#define VDEC2_RV_AI_Y_X                            0x0e09
#define VDEC2_RV_AI_U_X                            0x0e0a
#define VDEC2_RV_AI_V_X                            0x0e0b
// bit 15:0 will count up when rv_ai_mb finished when non zero
// and rv_ai_mb_finished_int will be generate when this is not zero
#define VDEC2_RV_AI_MB_COUNT                       0x0e0c
// For H264 I in PB picture Use -- dma type : h264_next_intra_dma
#define VDEC2_NEXT_INTRA_DMA_ADDRESS               0x0e0d
// Bit 0 -- constrained_intra_pred_flag for H264
#define VDEC2_IQIDCT_CONTROL                       0x0e0e
// Bit[31:19] Reserved
// Bit[18] iq_waiting
// Bit[17] iq_om_wr_idx
// Bit[16] iq_om_rd_idx
// Bit[15] iq_om_busy
// Bit[14] iq_om_2_busy 
// Bit[13] idx_fifo_0
// Bit[12] idx_fifo_1
// Bit[11] idx_fifo_2
// Bit[10] idx_fifo_3
// Bit[9] idx_fifo_4
// Bit[8] idx_fifo_5
// Bit[7] idx_fifo_6
// Bit[6] idx_fifo_7
// Bit[5:3] idx_fifo_wp
// Bit[2:0] idx_fifo_rp
#define VDEC2_IQIDCT_DEBUG_INFO_0                  0x0e0f
// For RTL Simulation Only
#define VDEC2_DEBLK_CMD                            0x0e10
// Bit[15+16] ds_mc_valid_2
// Bit[14+16] new_idct1_rd_idx_2
// Bit[13+16] new_idct1_wr_idx_2
// Bit[12+16] idct1_buff0_busy_2
// Bit[11+16] idct1_buff1_busy_2
// Bit[10+16] new_idct1_busy_2
// Bit[9+16] iq_om_8val_2
// Bit[8+16] idct1_pipe_busy_2
// Bit[7+16] wait_mb_left_finish_hold_2
// Bit[6+16] new_idct2_rd_idx_2
// Bit[5+16] new_idct2_wr_idx_2
// Bit[4+16] idct2_buff0_busy_2
// Bit[3+16] idct2_buff1_busy_2
// Bit[2+16] idct2_en_2
// Bit[1+16] new_idct2_busy_2
// Bit[0+16] new_idct1_ready_2
// Bit[15] ds_mc_valid_1
// Bit[14] new_idct1_rd_idx_1
// Bit[13] new_idct1_wr_idx_1
// Bit[12] idct1_buff0_busy_1
// Bit[11] idct1_buff1_busy_1
// Bit[10] new_idct1_busy_1
// Bit[9] iq_om_8val_1
// Bit[8] idct1_pipe_busy_1
// Bit[7] wait_mb_left_finish_hold_1
// Bit[6] new_idct2_rd_idx_1
// Bit[5] new_idct2_wr_idx_1
// Bit[4] idct2_buff0_busy_1
// Bit[3] idct2_buff1_busy_1
// Bit[2] idct2_en_1
// Bit[1] new_idct2_busy_1
// Bit[0] new_idct1_ready_1
#define VDEC2_IQIDCT_DEBUG_IDCT                    0x0e11
// bit 31 -- convas_enable
// bit 30:24 -- convas_x_count ( 8 pixels / 64 bits )
// bit 23:16 -- convas_y_count
// bit 15   -- dcac_dma_busy
// bit 14   -- dcac_dma_urgent
// bit 13:8 -- dcac_dma_count
// bit 7    -- dcac_dma_rw
// bit 6    -- dcac_skip_read_mode
// bit 5:0  -- dcac_dma_offset
#define VDEC2_DCAC_DMA_CTRL                        0x0e12
// when (convas_enable == 0 )
//   bit 31:0 dcac_dma_addr
// when (convas_enable == 1 )
//   bit 31:25 canvas_addr (7 bits)
//   bit 24:12 convas_y_start ( 13 btis )
//   bit 11:0  convas_x_start ( 12 btis )
#define VDEC2_DCAC_DMA_ADDRESS                     0x0e13
// bit 7:0 -- dcac_cpu_addr
#define VDEC2_DCAC_CPU_ADDRESS                     0x0e14
// bit 31:0 -- dcac_cpu_data
#define VDEC2_DCAC_CPU_DATA                        0x0e15
// bit 31:19 -- reserved
// bit 18:16 -- block_num_reg -- Read-Only 
// bit 15:0 -- dcac_mb_count
#define VDEC2_DCAC_MB_COUNT                        0x0e16
// bit 31:18 -- reserved
// For H264 :
//   bit 17:2 -- h264_quant 
//   bit 11:6 -- h264_quant_c 
//   bit  5:0 -- h264_quant_c 
// For VC1 :
//   bit    17 -- qindex_GT_8
//   bit    16 -- HalfQPStep
//   bit 15:12 -- eQuantMode 
//   bit 11:6  -- AltPQuant 
//   bit  5:0  -- PQuant 
//             
#define VDEC2_IQ_QUANT                             0x0e17
// bit 31:24  -- bitplane_width 
// bit 23:16  -- bitplane_height 
// bit 15:14  -- bitplane_start_x 
// bit 13:12  -- bitplane_start_y 
// bit 11:4   -- reserved
// bit 3:1    -- bitplane_type
// bit 0      -- bitplane_busy
#define VDEC2_VC1_BITPLANE_CTL                     0x0e18
//======================================
//  VCOP Control Register Bits
//
//======================================
    //`define IQIDCT_RESET	    16'h0001	    // Bit 0
//======================================
//  QP Control Register Bits
//
//======================================
// Duplicate Address:  When actually used
// please move to a different address
// `define FLD_DCT_TYPE	    16'h0100	    // Bit 8	0 = Frame DCT; 1 = field DCT
//
// Closing file:  iqidct_regs.h
//
//
// Reading file:  vcpu_regs.h
//
//========================================================================
//  VCPU module level register offset
//========================================================================
// -----------------------------------------------
// CBUS_BASE:  DOS_VDEC_VCPU_CBUS_BASE = 0x03
// -----------------------------------------------
#define HCODEC_MSP                                 0x0300
#define HCODEC_MPSR                                0x0301
#define HCODEC_MINT_VEC_BASE                       0x0302
#define HCODEC_MCPU_INTR_GRP                       0x0303
#define HCODEC_MCPU_INTR_MSK                       0x0304
#define HCODEC_MCPU_INTR_REQ                       0x0305
#define HCODEC_MPC_P                               0x0306
#define HCODEC_MPC_D                               0x0307
#define HCODEC_MPC_E                               0x0308
#define HCODEC_MPC_W                               0x0309
#define HCODEC_MINDEX0_REG                         0x030a
#define HCODEC_MINDEX1_REG                         0x030b
#define HCODEC_MINDEX2_REG                         0x030c
#define HCODEC_MINDEX3_REG                         0x030d
#define HCODEC_MINDEX4_REG                         0x030e
#define HCODEC_MINDEX5_REG                         0x030f
#define HCODEC_MINDEX6_REG                         0x0310
#define HCODEC_MINDEX7_REG                         0x0311
#define HCODEC_MMIN_REG                            0x0312
#define HCODEC_MMAX_REG                            0x0313
#define HCODEC_MBREAK0_REG                         0x0314
#define HCODEC_MBREAK1_REG                         0x0315
#define HCODEC_MBREAK2_REG                         0x0316
#define HCODEC_MBREAK3_REG                         0x0317
#define HCODEC_MBREAK_TYPE                         0x0318
#define HCODEC_MBREAK_CTRL                         0x0319
#define HCODEC_MBREAK_STAUTS                       0x031a
#define HCODEC_MDB_ADDR_REG                        0x031b
#define HCODEC_MDB_DATA_REG                        0x031c
#define HCODEC_MDB_CTRL                            0x031d
#define HCODEC_MSFTINT0                            0x031e
#define HCODEC_MSFTINT1                            0x031f
#define HCODEC_CSP                                 0x0320
#define HCODEC_CPSR                                0x0321
#define HCODEC_CINT_VEC_BASE                       0x0322
#define HCODEC_CCPU_INTR_GRP                       0x0323
#define HCODEC_CCPU_INTR_MSK                       0x0324
#define HCODEC_CCPU_INTR_REQ                       0x0325
#define HCODEC_CPC_P                               0x0326
#define HCODEC_CPC_D                               0x0327
#define HCODEC_CPC_E                               0x0328
#define HCODEC_CPC_W                               0x0329
#define HCODEC_CINDEX0_REG                         0x032a
#define HCODEC_CINDEX1_REG                         0x032b
#define HCODEC_CINDEX2_REG                         0x032c
#define HCODEC_CINDEX3_REG                         0x032d
#define HCODEC_CINDEX4_REG                         0x032e
#define HCODEC_CINDEX5_REG                         0x032f
#define HCODEC_CINDEX6_REG                         0x0330
#define HCODEC_CINDEX7_REG                         0x0331
#define HCODEC_CMIN_REG                            0x0332
#define HCODEC_CMAX_REG                            0x0333
#define HCODEC_CBREAK0_REG                         0x0334
#define HCODEC_CBREAK1_REG                         0x0335
#define HCODEC_CBREAK2_REG                         0x0336
#define HCODEC_CBREAK3_REG                         0x0337
#define HCODEC_CBREAK_TYPE                         0x0338
#define HCODEC_CBREAK_CTRL                         0x0339
#define HCODEC_CBREAK_STAUTS                       0x033a
#define HCODEC_CDB_ADDR_REG                        0x033b
#define HCODEC_CDB_DATA_REG                        0x033c
#define HCODEC_CDB_CTRL                            0x033d
#define HCODEC_CSFTINT0                            0x033e
#define HCODEC_CSFTINT1                            0x033f
#define HCODEC_IMEM_DMA_CTRL                       0x0340
#define HCODEC_IMEM_DMA_ADR                        0x0341
#define HCODEC_IMEM_DMA_COUNT                      0x0342
// bit[29:24] A_brst_num_imem
// bit[21:16] A_id_imem
// bit[11:0] wrrsp_count_imem (reserved)
#define HCODEC_WRRSP_IMEM                          0x0343
#define HCODEC_LMEM_DMA_CTRL                       0x0350
#define HCODEC_LMEM_DMA_ADR                        0x0351
#define HCODEC_LMEM_DMA_COUNT                      0x0352
// bit[29:24] A_brst_num_lmem
// bit[21:16] A_id_lmem
// bit[11:0] wrrsp_count_lmem 
#define HCODEC_WRRSP_LMEM                          0x0353
#define HCODEC_MAC_CTRL1                           0x0360
#define HCODEC_ACC0REG1                            0x0361
#define HCODEC_ACC1REG1                            0x0362
#define HCODEC_MAC_CTRL2                           0x0370
#define HCODEC_ACC0REG2                            0x0371
#define HCODEC_ACC1REG2                            0x0372
#define HCODEC_CPU_TRACE                           0x0380
//
// Closing file:  vcpu_regs.h
//
//
// Reading file:  vcpu_regs.h
//
//========================================================================
//  VCPU module level register offset
//========================================================================
// -----------------------------------------------
// CBUS_BASE:  DOS_VDEC_VCPU_CBUS_BASE = 0x03
// -----------------------------------------------
#define VDEC2_MSP                                  0x0300
#define VDEC2_MPSR                                 0x0301
#define VDEC2_MINT_VEC_BASE                        0x0302
#define VDEC2_MCPU_INTR_GRP                        0x0303
#define VDEC2_MCPU_INTR_MSK                        0x0304
#define VDEC2_MCPU_INTR_REQ                        0x0305
#define VDEC2_MPC_P                                0x0306
#define VDEC2_MPC_D                                0x0307
#define VDEC2_MPC_E                                0x0308
#define VDEC2_MPC_W                                0x0309
#define VDEC2_MINDEX0_REG                          0x030a
#define VDEC2_MINDEX1_REG                          0x030b
#define VDEC2_MINDEX2_REG                          0x030c
#define VDEC2_MINDEX3_REG                          0x030d
#define VDEC2_MINDEX4_REG                          0x030e
#define VDEC2_MINDEX5_REG                          0x030f
#define VDEC2_MINDEX6_REG                          0x0310
#define VDEC2_MINDEX7_REG                          0x0311
#define VDEC2_MMIN_REG                             0x0312
#define VDEC2_MMAX_REG                             0x0313
#define VDEC2_MBREAK0_REG                          0x0314
#define VDEC2_MBREAK1_REG                          0x0315
#define VDEC2_MBREAK2_REG                          0x0316
#define VDEC2_MBREAK3_REG                          0x0317
#define VDEC2_MBREAK_TYPE                          0x0318
#define VDEC2_MBREAK_CTRL                          0x0319
#define VDEC2_MBREAK_STAUTS                        0x031a
#define VDEC2_MDB_ADDR_REG                         0x031b
#define VDEC2_MDB_DATA_REG                         0x031c
#define VDEC2_MDB_CTRL                             0x031d
#define VDEC2_MSFTINT0                             0x031e
#define VDEC2_MSFTINT1                             0x031f
#define VDEC2_CSP                                  0x0320
#define VDEC2_CPSR                                 0x0321
#define VDEC2_CINT_VEC_BASE                        0x0322
#define VDEC2_CCPU_INTR_GRP                        0x0323
#define VDEC2_CCPU_INTR_MSK                        0x0324
#define VDEC2_CCPU_INTR_REQ                        0x0325
#define VDEC2_CPC_P                                0x0326
#define VDEC2_CPC_D                                0x0327
#define VDEC2_CPC_E                                0x0328
#define VDEC2_CPC_W                                0x0329
#define VDEC2_CINDEX0_REG                          0x032a
#define VDEC2_CINDEX1_REG                          0x032b
#define VDEC2_CINDEX2_REG                          0x032c
#define VDEC2_CINDEX3_REG                          0x032d
#define VDEC2_CINDEX4_REG                          0x032e
#define VDEC2_CINDEX5_REG                          0x032f
#define VDEC2_CINDEX6_REG                          0x0330
#define VDEC2_CINDEX7_REG                          0x0331
#define VDEC2_CMIN_REG                             0x0332
#define VDEC2_CMAX_REG                             0x0333
#define VDEC2_CBREAK0_REG                          0x0334
#define VDEC2_CBREAK1_REG                          0x0335
#define VDEC2_CBREAK2_REG                          0x0336
#define VDEC2_CBREAK3_REG                          0x0337
#define VDEC2_CBREAK_TYPE                          0x0338
#define VDEC2_CBREAK_CTRL                          0x0339
#define VDEC2_CBREAK_STAUTS                        0x033a
#define VDEC2_CDB_ADDR_REG                         0x033b
#define VDEC2_CDB_DATA_REG                         0x033c
#define VDEC2_CDB_CTRL                             0x033d
#define VDEC2_CSFTINT0                             0x033e
#define VDEC2_CSFTINT1                             0x033f
#define VDEC2_IMEM_DMA_CTRL                        0x0340
#define VDEC2_IMEM_DMA_ADR                         0x0341
#define VDEC2_IMEM_DMA_COUNT                       0x0342
// bit[29:24] A_brst_num_imem
// bit[21:16] A_id_imem
// bit[11:0] wrrsp_count_imem (reserved)
#define VDEC2_WRRSP_IMEM                           0x0343
#define VDEC2_LMEM_DMA_CTRL                        0x0350
#define VDEC2_LMEM_DMA_ADR                         0x0351
#define VDEC2_LMEM_DMA_COUNT                       0x0352
// bit[29:24] A_brst_num_lmem
// bit[21:16] A_id_lmem
// bit[11:0] wrrsp_count_lmem 
#define VDEC2_WRRSP_LMEM                           0x0353
#define VDEC2_MAC_CTRL1                            0x0360
#define VDEC2_ACC0REG1                             0x0361
#define VDEC2_ACC1REG1                             0x0362
#define VDEC2_MAC_CTRL2                            0x0370
#define VDEC2_ACC0REG2                             0x0371
#define VDEC2_ACC1REG2                             0x0372
#define VDEC2_CPU_TRACE                            0x0380
//
// Closing file:  vcpu_regs.h
//
//
// Reading file:  henc_regs.h
//
//========================================================================
//  MDEC module level register offset
//========================================================================
// -----------------------------------------------
// CBUS_BASE:  DOS_HCODEC_HENC_CBUS_BASE = 0x0a
// -----------------------------------------------
#define HCODEC_HENC_SCRATCH_0                      0x0ac0
#define HCODEC_HENC_SCRATCH_1                      0x0ac1
#define HCODEC_HENC_SCRATCH_2                      0x0ac2
#define HCODEC_HENC_SCRATCH_3                      0x0ac3
#define HCODEC_HENC_SCRATCH_4                      0x0ac4
#define HCODEC_HENC_SCRATCH_5                      0x0ac5
#define HCODEC_HENC_SCRATCH_6                      0x0ac6
#define HCODEC_HENC_SCRATCH_7                      0x0ac7
#define HCODEC_HENC_SCRATCH_8                      0x0ac8
#define HCODEC_HENC_SCRATCH_9                      0x0ac9
#define HCODEC_HENC_SCRATCH_A                      0x0aca
#define HCODEC_HENC_SCRATCH_B                      0x0acb
#define HCODEC_HENC_SCRATCH_C                      0x0acc
#define HCODEC_HENC_SCRATCH_D                      0x0acd
#define HCODEC_HENC_SCRATCH_E                      0x0ace
#define HCODEC_HENC_SCRATCH_F                      0x0acf
#define HCODEC_HENC_SCRATCH_G                      0x0ad0
#define HCODEC_HENC_SCRATCH_H                      0x0ad1
#define HCODEC_HENC_SCRATCH_I                      0x0ad2
#define HCODEC_HENC_SCRATCH_J                      0x0ad3
#define HCODEC_HENC_SCRATCH_K                      0x0ad4
#define HCODEC_HENC_SCRATCH_L                      0x0ad5
#define HCODEC_HENC_SCRATCH_M                      0x0ad6
#define HCODEC_HENC_SCRATCH_N                      0x0ad7
// bit [7:0] data_feed_buff_id
#define HCODEC_IE_DATA_FEED_BUFF_INFO              0x0ad8
//
// Closing file:  henc_regs.h
//
//
// Reading file:  vlc_regs.h
//
//========================================================================
//  VLC module level register offset
//========================================================================
// -----------------------------------------------
// CBUS_BASE:  DOS_HCODEC_VLC_CBUS_BASE = 0x0d
// -----------------------------------------------
// Bit[31:28] - henc_status
// Bit[27:8] - reserved
// Bit[7]    mc_hcmd_buff_enable
// Bit[6]    mc_hcmd_use_mc_hcmd_buff
// Bit[5]    mc_hcmd_use_mc_hcmd_hw_start
// Bit[4]    no_mc_out_null_non_skipped_mb
// Bit[3]    mc_out_even_skipped_mb
// Bit[2] - hcmd_enable
// Bit[1] - vlc_control_enable (0 will treat as soft_reset)
// Bit[0] - vlc_input_enable (enable input interface)
#define HCODEC_VLC_STATUS_CTRL                     0x0d00
// Bit[31:16] - Reserved
// Bit [15]  - enable_free_clk_mc_hcmd_buff
// Bit [14]  - enable_free_clk_reg
// Bit [13]  - enable_free_clk_stream
// Bit [12]  - enable_free_clk_pre_buff
// Bit [11]  - enable_free_clk_vb_buff
// Bit [10]  - enable_free_clk_dc_input
// Bit [9]   - enable_free_clk_input
// Bit [8]   - enable_free_clk_mv_cal
// Bit [7]   - enable_free_clk_status
// Bit [6]   - enable_free_clk_mc_dblk_cmd_if
// Bit [5]   - disable_mvd_enc_finished
// Bit [4]   - I16MB_share_ipred_mode_with_I4MB
// Bit [3]   - fixed_picture_qp
// Bit [2]   - use_set_b8_mode ( not used now)
// Bit [1]   - use_set_mb_skip_run
// Bit [0]   - pop_coeff_even_all_zero
#define HCODEC_VLC_CONFIG                          0x0d01
// --------------------------------------------
// Bitstream DDR Interface
// --------------------------------------------
#define HCODEC_VLC_VB_START_PTR                    0x0d10
#define HCODEC_VLC_VB_END_PTR                      0x0d11
#define HCODEC_VLC_VB_WR_PTR                       0x0d12
// Read Only, VLC_VB_SW_RD_PTR or VLC_VB_HW_RD_PTR
#define HCODEC_VLC_VB_RD_PTR                       0x0d13
#define HCODEC_VLC_VB_SW_RD_PTR                    0x0d14
// Read Only
#define HCODEC_VLC_VB_LEFT                         0x0d15
// VB FIFO Control
// bit  [31:24] vb_full_int_enable_cpu[7:0] 
// bit  [23:16] vb_full_int_enable_amrisc[7:0] 
//   -bit 23 Video BUFFER LEFT < 0x400 Bytes
//   -bit 22 Video BUFFER LEFT < 0x200 Bytes
//   -bit 21 Video BUFFER LEFT < 0x100 Bytes
//   -bit 20 Video BUFFER LEFT < 0x80 Bytes
//   -bit 19 Video BUFFER LEFT < 0x40 Bytes
//   -bit 18 Video BUFFER LEFT < 0x20 Bytes
//   -bit 17 vbfifo left  < 16 double words (8x64bits)
//   -bit 16 vbfifo left  < 8 double words (4x64bits)
// bit  [15]    wr_ptr_int_enable_cpu
// bit  [14]    wr_ptr_int_enable_amrisc
// bit  [13]    wr_ptr_int (Read Only, write 1 will clear)
// bit  [12]    vb_full_int_enable_cpu(Read Only)
// bit  [11]    vb_full_int_enable_amrisc(Read Only)
// bit  [10]    reserved
// bit  [9]     use_vb_hw_rd_ptr
// bit  [8]     vb_always_ready Set to 1 to ignore vb_level blocking DDR write
// bit  [7]     vb_ready_for_transfer (Read Only)
// bit  [6]     data_ready_for_transfer (Read Only)
// bits [5:3]   vb_endian       Set VB Endian inside DDR memory 
// bit  [2]     vb_write_busy   Read Only - indicate DDR write busy
// bit  [1]     vb_write_en     Set to 1 to enable writing data to DDR memory
// bit  [0]     vb_soft_reset   Soft reset  
#define HCODEC_VLC_VB_CONTROL                      0x0d16
// bit 31    transfer_length 0 - 32x64 Bits per request, 1 - 16x64 Bits per request  // default : 0
// bit 30    A_urgent  // default : 0
// bit 29:24 A_brst_num // default : 0x3f
// bit 23:22 reserved
// bit 21:16 A_id  // default : 0x20 
// bit 15:0  vb_left_hold // default : 0 
#define HCODEC_VLC_VB_MEM_CTL                      0x0d17
// vb_wr_ptr address to generate interrupt
#define HCODEC_VLC_VB_INT_PTR                      0x0d18
// bit[31:12] reserved
// bit[11:0] vlc_wrrsp_count
#define HCODEC_VLC_WRRSP                           0x0d19
#define HCODEC_VLC_TOTAL_BYTES                     0x0d1a
// bit  [31:26] reserved
// bit  [25]    vb_flush
// bit  [24]    vb_reg_ready  
// bit  [23:16] vb_buff_left     -- Read only
// bit  [15:8]  vb_buff_wr_point -- RW
// bit  [7:0]   vb_buff_rd_point -- RW
#define HCODEC_VLC_VB_BUFF                         0x0d1b
// bit[31]    flush_vlc_pre_buff
// bit[30:27] reserved
// bit[26:24] vb_pre_buff_level
// bit[23:0]  vb_pre_buff_data[55:32] 
#define HCODEC_VLC_VB_PRE_BUFF_HI                  0x0d1c
// bit[31:0] vb_pre_buff_data[31:0]
#define HCODEC_VLC_VB_PRE_BUFF_LOW                 0x0d1d
// bit[31]    stream_encap_enable  // 0x0000(00-03) will be changed to 0x000003(00-03) if enabled
// bit[30:29] stream_encap_delay   // delay bytes for encap used 
// bit[28:24] stream_buff_point
// bit[23:0]  stream_buff_data 
#define HCODEC_VLC_STREAM_BUFF                     0x0d1e
// bit[31]    push_stream_block - Read Only (Will set if vb_buff full)
// bit[30]    push_stream_busy  - Read Only (busy when output one byte from stream_buf (max 2 clocks for 8 bits push)
// bit[29:28] stream_encap_status - Read Only
// bit[27:21] reserved
// Long Mode : (Amrisc need movilo and mvihi high to set stream_info)
//   bit[20:16] push_stream_long_length (0 or 31 : Mid or Short mode)
//   bit[15:0]  push_stream_data
// Mid Mode : (Amrisc need movi to set stream_info) 
//   bit[15:12]] push_stream_mid_length (1-12 : mid mode active, 0-short mode, 15 - byte align)
//   bit[11:0]  push_stream_data
// Short Mode : (Amrisc can use mtspi to push stream directely)
//   bit[7:5] push_stream_short_length (0-5 : short length, else - invalid)
//   bit[4:0]  push_stream_data
#define HCODEC_VLC_PUSH_STREAM                     0x0d1f
// bit[15:8] ELEMENT_LENGTH
// bit[7:1]  reserved
// bit[0]  Write - push start, Read - Push Busy
#define HCODEC_VLC_PUSH_ELEMENT                    0x0d20
#define HCODEC_VLC_ELEMENT_DATA                    0x0d21
// --------------------------------------------
// Picture VLC 
// --------------------------------------------
// (&(int|(~AND_enable))|(|(int&OR_enable)))
// bit[31]    OR interrupt Enable Reserved
// bit[30]    OR interrupt Enable for mv_busy
// bit[29]    OR interrupt Enable for b8_mode_busy
// bit[28]    OR interrupt Enable for mb_skip_run_busy
// bit[27]    OR interrupt Enable for cbp_busy
// bit[26]    OR interrupt Enable for Reserved
// bit[25]    OR interrupt Enable for Reserved
// bit[24]    OR interrupt Enable for mb_info_busy
// bit[23]    AND interrupt Enable Reserved
// bit[22]    AND interrupt Enable for mv_busy
// bit[21]    AND interrupt Enable for b8_mode_busy
// bit[20]    AND interrupt Enable for mb_skip_run_busy
// bit[19]    AND interrupt Enable for cbp_busy 
// bit[18]    AND interrupt Enable for Reserved
// bit[17]    AND interrupt Enable for Reserved        
// bit[16]    AND interrupt Enable for mb_info_busy
// bit[15]    OR interrupt Enable Reserved
// bit[14]    OR interrupt Enable for mvd
// bit[13]    OR interrupt Enable for b8_mode
// bit[12]    OR interrupt Enable for mb_skip_run
// bit[11]    OR interrupt Enable for cbp_ready
// bit[10]    OR interrupt Enable for c_ipred_mode_ready
// bit[9]     OR interrupt Enable for ipred_mode_ready
// bit[8]     OR interrupt Enable for mb_info_ready
// bit[7]     AND interrupt Enable Reserved
// bit[6]     AND interrupt Enable for mvd
// bit[5]     AND interrupt Enable for b8_mode
// bit[4]     AND interrupt Enable for mb_skip_run
// bit[3]     AND interrupt Enable for cbp_ready
// bit[2]     AND interrupt Enable for c_ipred_mode_ready
// bit[1]     AND interrupt Enable for ipred_mode_ready
// bit[0]     AND interrupt Enable for mb_info_ready
#define HCODEC_VLC_INT_CONTROL                     0x0d30
// Bit[31:16] picture_height
// Bit[15:0]  picture_width
#define HCODEC_VLC_PIC_SIZE                        0x0d31
// [31:16] Reserved
// [15:3] pic_width_in_mbs_minus1
// [2:0]  picture_type 
#define HCODEC_VLC_PIC_INFO                        0x0d32
// Bit[31:16] MB_NR
// Bit[15:8] MBY
// Bit[7:0] MBX
#define HCODEC_VLC_PIC_POSITION                    0x0d33
// Bit[31] MV_busy
// Bit[30:6] Reserved
// Bit[15] Reserved
// Bit[14] vlc_input_MV_busy
// Bit[13] vlc_input_b8_mode_busy
// Bit[12] vlc_input_mb_skip_run_busy
// Bit[11] vlc_input_cbp_busy
// Bit[10] Reserved
// Bit[9]  Reserved
// Bit[8] vlc_input_mb_info_busy
// Bit[7] Reserved
// Bit[6] mvd
// Bit[5] b8_mode
// Bit[4] mb_skip_run
// Bit[3] cbp
// Bit[2] c_ipred_mode
// Bit[1] ipred_mode
// Bit[0] mb_info ( mb_type, mb_x, mb_y)
#define HCODEC_VLC_INPUT_STATUS                    0x0d34
// Bit[31:28] detected_mb_type
// Bit[27:16] mb_y 
// Bit[15:4]  mb_x 
// Bit[3:0]   mb_type
#define HCODEC_VLC_MB_INFO                         0x0d35
// commnad 0 -- no pending
// normal command + 1 is pending command
//
// bit 31:28 -- pending command 7
// bit 27:24 -- pending command 6
// bit 23:20 -- pending command 5
// bit 19:16 -- pending command 4
// bit 15:12 -- pending command 3
// bit 11:8  -- pending command 2
// bit  7:4  -- pending command 1
// bit  3:0  -- pending command 0
#define HCODEC_VLC_ENC_PEND_CMD                    0x0d36
// For I Slice
// Bit[31:16] Reserved
// Bit[15:0] IntraType 
#define HCODEC_HENC_TOP_INFO_0                     0x0d37
#define HCODEC_HENC_LEFT_INFO_0                    0x0d38
// For I Slice
// Bit[31:24] V_nnz
// Bit[23:16] U_nnz
// Bit[15:0]  Y_nnz 
#define HCODEC_HENC_TOP_INFO_1                     0x0d39
#define HCODEC_HENC_LEFT_INFO_1                    0x0d3a
// bit[63:0] ipred_mode
#define HCODEC_VLC_IPRED_MODE_HI                   0x0d3b
#define HCODEC_VLC_IPRED_MODE_LO                   0x0d3c
// bit[15:8] SE delta quant 
// bit[7:0]  UE delta quant
#define HCODEC_VLC_DELTA_QP                        0x0d3d
// bit[31:16] Reserved
// bit[15:12] Reserved
// bit[11:8] c_ipred_mode 
// bit[7:0] cbp
#define HCODEC_VLC_MB_HEADER_INFO                  0x0d3e
// bit[31:16] mb_skip_run
// bit[15:0]  b8_mode
#define HCODEC_VLC_P_MB_HEADER_INFO                0x0d3f
// bit[31]    write_ptr_update
// bit[30]    read_ptr_update
// bit[29:20] coeff_buf_level
// bit[19:10] coeff_buf_write_ptr
// bit[9:0]   coeff_buf_read_ptr
#define HCODEC_VLC_COEFF_BUF_STATUS                0x0d40
// bit[31:10] Reserved
// bit[9:0] read_req_addr
#define HCODEC_VLC_COEFF_RD_REQ                    0x0d41
// bit[20]   - coeff_buf_read_finished
// bit[19]   - coeff_first
// bit[18:4] - coeff_level 
// bit[3:0]  - coeff_run 
#define HCODEC_VLC_COEFF                           0x0d42
// bit[31]    - coeff_info_ready
// bit[30:25] - Reserved
// bit[24:15] - block_begin_addr
// bit[14:11] - trailing_one_sign
// bit[10:6]  - total_coeff 
// bit[5:4]   - trailing_ones 
// bit[3:0]   - total_zeros
#define HCODEC_VLC_COEFF_INFO                      0x0d43
// bit[31]    write_ptr_update
// bit[30]    read_ptr_update
// bit[29:25] Reserved
// bit[24:20] dc_buf_level -- 0-16
// bit[19:15] Reserved
// bit[14:10] dc_buf_write_ptr
// bit[9:5]   Reserved
// bit[4:0]   dc_buf_read_ptr
#define HCODEC_VLC_DC_BUF_STATUS                   0x0d44
// bit[31:10] Reserved
// bit[9:4]   Reserved
// bit[3:0]   read_req_addr
#define HCODEC_VLC_DC_RD_REQ                       0x0d45
// bit[31:17] - Reserved
// bit[16]   - dc_first
// bit[15:1] - dc_level 
// bit[0]    - dc_type  0 - CDC, 1 - LDC
#define HCODEC_VLC_DC                              0x0d46
// bit[31]    - dc_info_ready
// bit[30:25] - Reserved
// bit[24:20] - Reserved
// bit[19:15] - dc_idx_begin_addr
// bit[14:11] - dc_trailing_one_sign
// bit[10:6]  - dc_total_coeff 
// bit[5:4]   - dc_trailing_ones 
// bit[3:0]   - dc_total_zeros
#define HCODEC_VLC_DC_INFO                         0x0d47
// bit[31:4]  - Reserved
// bit[3:0]   - mv_rw_idx  (auto increment when read/write VLC_MV) 
#define HCODEC_VLC_MV_INDEX                        0x0d48
// bit[31:16] - MVY
// bit[15:0]  - MVX
#define HCODEC_VLC_MV                              0x0d49
// bit[31:16] - MVY
// bitp15:0]  - MVX
// Write to HENC_TOP_MV_0 will cause previous U->UL, UR->U, and UR write
// Read will read U MV only 
#define HCODEC_HENC_TOP_MV_0                       0x0d4a
#define HCODEC_HENC_TOP_MV_1                       0x0d4b
#define HCODEC_HENC_TOP_MV_2                       0x0d4c
#define HCODEC_HENC_TOP_MV_3                       0x0d4d
#define HCODEC_HENC_LEFT_MV_0                      0x0d4e
#define HCODEC_HENC_LEFT_MV_1                      0x0d4f
#define HCODEC_HENC_LEFT_MV_2                      0x0d50
#define HCODEC_HENC_LEFT_MV_3                      0x0d51
// Bit[31:1] Reserved
// Bit[0] top_left_mv_ready
#define HCODEC_TOP_LEFT_READY                      0x0d52
// Bit[31:16] Reserved
// Bit[15:0] mb_skip_run
#define HCODEC_MB_SKIP_RUN                         0x0d53
// Bit[31:16] Reserved
// Bit[15]    Reserved
// Bit[14:13] rd_struct // 00 - frame, 10 - top field, 11 - bottom field
// Bit[12:11] wr_struct // 00 - frame, 10 - top field, 11 - bottom field
// Bit[10:5]  mv_buff_id
// Bit[4:0]   mv_ref
#define HCODEC_VLC_HCMD_CONFIG                     0x0d54
// Bit[9:0] h264_dblk_info
#define HCODEC_VLC_HCMD_DBLK_INFO                  0x0d55
// Bit[3:0] vlc_dbg_idx
#define HCODEC_VLC_DBG_IDX                         0x0d56
// Read Only
#define HCODEC_VLC_DBG_READ                        0x0d57
#define HCODEC_VLC_JPEG_CTRL                       0x0d58
#define HCODEC_VLC_JPEG_COEFF_BUF_STAT             0x0d59
#define HCODEC_VLC_HUFFMAN_ADDR                    0x0d5a
#define HCODEC_VLC_HUFFMAN_DATA                    0x0d5b
// bit[31:0] enc_mv_bits - including b8_mode and mvd
#define HCODEC_VLC_ENC_MV_BITS                     0x0d5c
// bit[31:0] enc_coeff_bits - including cbp, token, trailing_sign, coeff_enc, h264_totzeros, h264_run
#define HCODEC_VLC_ENC_COEFF_BITS                  0x0d5d
//
// Closing file:  vlc_regs.h
//
//
// Reading file:  qdct_regs.h
//
//========================================================================
//  QDCT module level register offset
//========================================================================
// -----------------------------------------------
// CBUS_BASE:  DOS_HCODEC_QDCT_CBUS_BASE = 0x0f
// -----------------------------------------------
// bit[31:28] - mb_info_state
#define HCODEC_QDCT_STATUS_CTRL                    0x0f00
// bit[18]    - enable_free_clk_sad_top
// bit[17]    - enable_free_clk_ie_top
// bit[16]    - enable_free_clk_ie_sub
// bit[15]    - enable_free_clk_mc_out
// bit[14]    - enable_free_clk_i_pred_top
// bit[13]    - enable_free_clk_idct_top
// bit[12]    - enable_free_clk_iq_top
// bit[11]    - enable_free_clk_q_top
// bit[10]    - enable_free_clk_dc_buff_8
// bit[9]     - enable_free_clk_dct_top
// bit[8]     - enable_free_clk_mb_info
// bit[7]     - enable_free_clk_mb_buff
// bit[6]     - enable_free_clk_reg
// bit[5]     - ignore_1_include_2nd_half_c
// bit[4]     - ignore_1_include_2nd_half
// bit[3]     - ignore_t_p8x8
// bit[2]     - not_ignore_dc
// bit[1]     - ignore_small_lac_intra
// bit[0]     - disable_fast_zero_block
#define HCODEC_QDCT_CONFIG                         0x0f01
// bit[31]    - ignore_lac_coeff_en
// bit[30:26] - ignore_lac_coeff_else
// bit[25:21] - ignore_lac_coeff_2 
// bit[20:16] - ignore_lac_coeff_1 
// bit[15]    - ignore_cac_coeff_en
// bit[14:10] - ignore_cac_coeff_else
// bit[9:5]   - ignore_cac_coeff_2 
// bit[4:0]   - ignore_cac_coeff_1 
#define HCODEC_IGNORE_CONFIG                       0x0f02
// bit[31]    - ignore_t_lac_coeff_en
// bit[30:26] - ignore_t_lac_coeff_else
// bit[25:21] - ignore_t_lac_coeff_2 
// bit[20:16] - ignore_t_lac_coeff_1 
// bit[15:0]  - Reserved
#define HCODEC_IGNORE_CONFIG_2                     0x0f03
// --------------------------------------------
// MB DATA DDR Interface
// --------------------------------------------
#define HCODEC_QDCT_MB_START_PTR                   0x0f10
#define HCODEC_QDCT_MB_END_PTR                     0x0f11
#define HCODEC_QDCT_MB_WR_PTR                      0x0f12
#define HCODEC_QDCT_MB_RD_PTR                      0x0f13
#define HCODEC_QDCT_MB_LEVEL                       0x0f14
// bit  [31]    reserved
// bit  [30]    no_wait_after_q_cdc
// bit  [29]    ie_start_int_enable
// bit  [28]    ignore_t_p8x8
// bit  [27]    zero_mc_out_null_non_skipped_mb
// bit  [26]    no_mc_out_null_non_skipped_mb
// bit  [25]    mc_out_even_skipped_mb
// bit  [24]    mc_out_wait_cbp_ready
// bit  [23]    mc_out_wait_mb_type_ready
// bit  [22]    i_pred_int_enable
// bit  [21]    intra_sat8_enable
// bit  [20]    ie_sub_enable
// bit  [19]    i_pred_enable
// bit  [18]    iq_enable
// bit  [17]    idct_enable
// bit  [16]    no_zero_coeff_mb
// bit  [15]    add_zero_coeff_block
// bit  [14]    mb_pause_enable
// bit  [13]    q_enable
// bit  [12]    dct_enable
// bit  [11]    ignore_magic_word
// bit  [10]    mb_info_en
// bit  [9]     mb_info_soft_reset
// bit  [8]     mb_always_ready Set to 1 to ignore mb_level blocking DDR read
// bit  [7]     mb_ready_for_transfer (Read Only)
// bit  [6]     data_ready_for_transfer (Read Only)
// bits [5:3]   mb_endian       Set MB Endian inside DDR memory 
// bit  [2]     mb_read_busy   Read Only - indicate DDR read busy
// bit  [1]     mb_read_en     Set to 1 to enable reading data from DDR memory
// bit  [0]     mb_soft_reset   Soft reset  
#define HCODEC_QDCT_MB_CONTROL                     0x0f15
// bit 31    transfer_length 0 - 32x64 Bits per request, 1 - 16x64 Bits per request  // default : 0
// bit 30    A_urgent  // default : 0
// bit 29:24 A_brst_num // default : 0x3f
// bit 23    reserved
// bit 22    read_till_zero
// bit 21:16 A_id  // default : 0x21 
// bit 15:0  mb_level_hold // default : 0 
#define HCODEC_QDCT_MB_MEM_CTL                     0x0f16
// bit  [31:24] reserved
// bit  [23:16] vb_buff_level     -- Read only
// bit  [15:8]  vb_buff_wr_point -- RW
// bit  [7:0]   vb_buff_rd_point -- RW
#define HCODEC_QDCT_MB_BUFF                        0x0f17
// bit [31:0] mb infor data begin magic word - default : 0xa55aaa55
#define HCODEC_QDCT_MB_MAGIC_WORD                  0x0f18
// Read Only Register
// bit[19]   dct_ready_1
// bit[18]   dct_ready_0
// bit[17]   dct_rd_idx
// bit[16]   dct_wr_idx
// bit[15]   dct_srdy
// bit[14]   dct_rrdy
// bit[13]   Reserved
// bit[12:8] dct_block_number 
// bit[7:4]  dct_rw_addr 
// bit[3:0]  dct_status
#define HCODEC_QDCT_DCT_STATUS                     0x0f19
// bit[3:0]  q_status
#define HCODEC_QDCT_Q_STATUS                       0x0f1a
// bit[31:3] Reserved
// bit[2:0]  picture_type
#define HCODEC_QDCT_PIC_INFO                       0x0f1b
// bit[31:28] Reserved
// bit[27:22] I_pic_quant_c
// bit[21:16] I_pic_quant
// bit[15]    reserved
// bit[14:12] quant_rem_c
// bit[11:8]  quant_per_c
// bit[7]     reserved
// bit[6:4]   quant_rem
// bit[3:0]   quant_per
#define HCODEC_QDCT_Q_QUANT_I                      0x0f1c
// bit[31:28] Reserved
// bit[27:22] P_pic_quant_c
// bit[21:16] P_pic_quant
// bit[15]    reserved
// bit[14:12] quant_rem_c
// bit[11:8]  quant_per_c
// bit[7]     reserved
// bit[6:4]   quant_rem
// bit[3:0]   quant_per
#define HCODEC_QDCT_Q_QUANT_P                      0x0f1d
// bit[31]    mb_info_pause
// bit[30:16] pause_mby
// bit[15:0]  pause_mbx
#define HCODEC_QDCT_MB_PAUSE_CTL                   0x0f1e
// bit[31]   top_control_ready_i_pred
// bit[30:28]top_dma_status   
// bit[27]   top_control_ready_ie
// bit[26:24]Reserved
// bit[23]   ul_mb
// bit[22]   right_mb
// bit[21]   top_mb
// bit[20]   left_mb
// bit[19:8] mb_x
// bit[7:6]  i_pred_ref_idx_L 
// bit[5:4]  i_pred_ref_idx_UL 
// bit[3:2]  i_pred_ref_idx_U
// bit[1:0]  i_pred_ref_idx_UR 
#define HCODEC_QDCT_TOP_CONTROL                    0x0f1f
// bit[31:0] top_base_addr - DDR Memory start address for save top Pixel
#define HCODEC_QDCT_TOP_BASE_MEM                   0x0f20
// bit 15:13 Reserved
// bit 12    A_urgent  // default : 0
// bit 11:6  A_brst_num // default : 0x3f
// bit 5:0   A_id  // default : 0x22
#define HCODEC_QDCT_TOP_MEM_CTL                    0x0f21
// bit [11:0] top_wrrsp_count
#define HCODEC_QDCT_TOP_WRRSP                      0x0f22
// Bit[3:0] qdct_dbg_idx
#define HCODEC_QDCT_DBG_IDX                        0x0f23
// Read Only
#define HCODEC_QDCT_DBG_READ                       0x0f24
#define HCODEC_QDCT_JPEG_CTRL                      0x0f25
#define HCODEC_QDCT_JPEG_X_START_END               0x0f26
#define HCODEC_QDCT_JPEG_Y_START_END               0x0f27
#define HCODEC_QDCT_JPEG_QUANT_ADDR                0x0f28
#define HCODEC_QDCT_JPEG_QUANT_DATA                0x0f29
#define HCODEC_QDCT_JPEG_SOF_RESUME                0x0f2a
#define HCODEC_QDCT_JPEG_DCT_STATUS0               0x0f2b
#define HCODEC_QDCT_JPEG_DCT_STATUS1               0x0f2c
#define HCODEC_QDCT_JPEG_DCT_COEFF01               0x0f2d
#define HCODEC_QDCT_JPEG_DCT_COEFF23               0x0f2e
#define HCODEC_QDCT_JPEG_DCT_COEFF45               0x0f2f
#define HCODEC_QDCT_JPEG_DCT_COEFF67               0x0f30
#define HCODEC_QDCT_JPEG_DCT_COEFF89               0x0f31
// IE/ME share same cbus_base as QDCT
// 
// bit[31]  active_ur_block
// bit[30]  active_ul_block
// bit[9]   ie_c_wait_ie_pause
// bit[8:4] max_ie_result_buff_count 
// bit[3]   ie_wait_for_ie_result  // use for (max_ie_result_buff_count == 0) to wait every block
// bit[2]   reserved
// bit[1]   ie_enable
// bit[0]   ie_soft_reset
#define HCODEC_IE_CONTROL                          0x0f40
// bit[31:12] Reserved
// bit[11:0]  mb_y
#define HCODEC_IE_MB_POSITION                      0x0f41
// bit[31:16] me_skip_run
// bit[15:8]  reserved
// bit [7:4]  me_b8_mode
// bit [3:0]  ie_me_mb_type
#define HCODEC_IE_ME_MB_INFO                       0x0f42
// bit[3]   ie_result_buff_enable
// bit[2]   ie_result_buff_soft_reset
// bit[1]   sad_enable
// bit[0]   sad_soft_reset
#define HCODEC_SAD_CONTROL                         0x0f43
// bit[31:16] - ie_result_buff_count - read only
// bit[14:12] -current_ie_result (pred_mode) - read only
// bit[11]  top_control_data_buff_wr_ptr - rd/wr 
// bit[10]  top_control_data_buff_rd_ptr - rd/wr 
// bit[9:5] ie_result_buff_wr_ptr        - rd/wr
// bit[4:0] ie_result_buff_rd_ptr        - rd/wr
#define HCODEC_IE_RESULT_BUFFER                    0x0f44
// bit[63:0] ie_i4_pred_mode
#define HCODEC_IE_I4_PRED_MODE_HI                  0x0f45
#define HCODEC_IE_I4_PRED_MODE_LO                  0x0f46
// bit [31:9] reserved
// bit [8:4] i_pred_block_number
// bit [3:0] ie_c_pred_mode
#define HCODEC_IE_C_PRED_MODE                      0x0f47
// 31:16 - Left, 0-select ie_pixel, 1-select mc_data_out
// 15:0  - Top,  0-select ie_pixel, 1-select mc_data_out
#define HCODEC_IE_CUR_REF_SEL                      0x0f48
// bit[31]  enable_f_skip_1_step_3
// bit[30]  enable_f_skip_1_step_2
// bit[29]  enable_f_skip_1_step_1
// bit[28]  step_3_enable
// bit[27]  step_2_sub_pixel
// bit[26]  always_f_skip_step_3 
// bit[25]  always_f_skip_step_2 
// bit[24]  always_f_skip_step_1
// bit[23]  half_pixel_only
// bit[22:11] reserved
// bit[10:9] mv_flexable_ctl 00:0x40, 01:0x80, 10:0xc0, 11 : 0x100
// bit[8]   no_md_ab_rd
// bit[7]   use_dct_state
// bit[6]   enable_free_clk_me_ctl
// bit[5]   enable_free_clk_me_ab
// bit[4]   enable_free_clk_me_cb
// bit[3]   reserved
// bit[2]   me_done_int_enable
// bit[1]   me_enable
// bit[0]   me_soft_reset
#define HCODEC_ME_CONTROL                          0x0f49
// bit[31:28] Reserved
// bit[27:16] me_start_mby
// bit[15:12] Reserved
// bit[11:0]  me_start_mbx
#define HCODEC_ME_START_POSITION                   0x0f4a
// bit [31:28] me_status - Read only
// bit [27:24] me_cb_status  // current buffer
// bit [23:20] me_ab_status  // anc buffer
// bit [19]    Reserved
// bit [18:16] me_ab_wr_ptr  // read only
// bit [15:4]  me_last_mbx 
// bit [3:1]   me_ab_rd_ptr  // read only
// bit [0]     me_action
#define HCODEC_ME_STATUS                           0x0f4b
// all Read-only
// bit [31:28] Reserved
// bit [27:16] me_ab_mbx
// bit [15:14] me_cb_wr_ptr
// bit [13:12] me_cb_rd_ptr
// bit [11:0]  me_cb_mbx
#define HCODEC_ME_DEBUG                            0x0f4c
// bit[29:24] step_3_skip_line 
// bit[23:18] step_2_skip_line 
// bit[17:12] step_1_skip_line 
// bit[11:6]  step_0_skip_line 
// bit[5:0]   read_skip_line 
#define HCODEC_ME_SKIP_LINE                        0x0f4d
// bit 15:13 Reserved
// bit 12    A_urgent  // default : 0
// bit 11:6  A_brst_num // default : 0x3f
// bit 5:0   A_id  // default : 0x23
#define HCODEC_ME_AB_MEM_CTL                       0x0f4e
// bit[31:24] anc_pic_canvas
// bit[23:12] max_me_mby_num
// bit[11:0]  max_me_mbx_num 
#define HCODEC_ME_PIC_INFO                         0x0f4f
// bit [23:12] me_sad_enough_1
// bit [11:0]  me_sad_enough_0
#define HCODEC_ME_SAD_ENOUGH_01                    0x0f50
// bit [23:12] me_sad_enough_3
// bit [11:0]  me_sad_enough_2
#define HCODEC_ME_SAD_ENOUGH_23                    0x0f51
// bit [21:10] me_step0_big_sad
// bit [9:5] me_step0_close_mv_y 
// bit [4:0] me_step0_close_mv_x 
#define HCODEC_ME_STEP0_CLOSE_MV                   0x0f52
// bit[31:24] force_skip_sad_3
// bit[23:16] force_skip_sad_2
// bit[15:08] force_skip_sad_1
// bit[07:00] force_skip_sad_0
#define HCODEC_ME_F_SKIP_SAD                       0x0f53
// bit[31:24] force_skip_weight_3
// bit[23:16] force_skip_weight_2
// bit[15:08] force_skip_weight_1
// bit[07:00] force_skip_weight_0
#define HCODEC_ME_F_SKIP_WEIGHT                    0x0f54
// Merge when (
//              (flex & me_merge_flex_en) | 
//              (big_sad & me_merge_sad_en)|
//              ((~me_merge_flex_en)&(~me_merge_sad_en))
//            ) & 
//            ( small_mv_diff |(~me_merge_small_mv_en))
//            & (me_merge_flex_en | me_merge_sad_en | me_merge_small_mv_en)
// bit[31]   me_merge_mv_en_16
// bit[30]   me_merge_small_mv_en_16
// bit[29]   me_merge_flex_en_16
// bit[28]   me_merge_sad_en_16
// bit[27]   me_merge_mv_en_8
// bit[26]   me_merge_small_mv_en_8
// bit[25]   me_merge_flex_en_8
// bit[24]   me_merge_sad_en_8
// bit[23:18] me_merge_mv_diff_16
// bit[17:12] me_merge_mv_diff_8
// bit[11:0] me_merge_min_sad
#define HCODEC_ME_MV_MERGE_CTL                     0x0f55
// bit[31:24] mv_step_weight_1 
// bit[23:16] mv_pre_weight_1 
// bit [15:0] mv_step_weight_0
// bit[7:0]   mv_pre_weight_0 
#define HCODEC_ME_MV_WEIGHT_01                     0x0f56
// bit[31:24] mv_step_weight_3 
// bit[23:16] mv_pre_weight_3
// bit[15:8]  mv_step_weight_2 
// bit[7:0]   mv_pre_weight_2
#define HCODEC_ME_MV_WEIGHT_23                     0x0f57
// bit[31:24] me_sad_range_inc_3
// bit[23:16] me_sad_range_inc_2
// bit[15:8] me_sad_range_inc_1
// bit[7:0] me_sad_range_inc_0
#define HCODEC_ME_SAD_RANGE_INC                    0x0f58
// bit[31:19]  reserved
// bit[18]     sub_relative_any_1_en
// bit[17]     sub_relative_any_2_en
// bit[16]     sub_relative_any_3_en
// bit[15]     sub_relative_any_4_en
// bit[14]     sub_relative_any_h_en
// bit[13]     sub_make_non_flex_fix
// bit[12]     sub_make_big_non_flex_fix
// bit[11:8]   sub_normal_mv_diff_16
// bit[7:4]    sub_normal_mv_diff_8
// bit[3:2]    Reserved
// bit[1]      sub_merge_enable_16
// bit[0]      sub_merge_enable_8
#define HCODEC_ME_SUB_MERGE_CTL                    0x0f59
// bit[31:28]  sub_ref_mv_diff_near
// bit[27:24]  sub_ref_mv_diff_near_flex
// bit[23:20]  sub_ref_mv_diff
// bit[19:16]  sub_ref_mv_diff_flex
// bit[15:8]   sub_ref_mv_near_weight
// bit[7:0]    sub_ref_mv_weight
#define HCODEC_ME_SUB_REF_MV_CTL                   0x0f5a
// bit[31:24]  sub_weight_max_sad
// bit[23:16]  sub_any_range_sad
// bit[15:8]   sub_any_min_sad
// bit[7:0]    sub_any_max_sad
#define HCODEC_ME_SUB_ANY_WEIGHT_SAD               0x0f5b
// bit[31:24]  sub_fix_sad
// bit[23:16]  sub_fix_diff_sad
// bit[15:8]   sub_sad_flex_adj
// bit[7:0]    sub_big_non_flex_fix_sad
#define HCODEC_ME_SUB_FIX_SAD                      0x0f5c
// bit[31:24]  sub_fix_min_sad
// bit[23:16]  sub_fix_min_diff_sad
// bit[15:8]   sub_fix_min_sad_2
// bit[7:0]    sub_fix_min_diff_sad_2
#define HCODEC_ME_SUB_FIX_MIN_SAD                  0x0f5d
// bit[31:24]  sub_snap_to_ref_max_sad
// bit[23]     sub_snap_to_ref_non_flex
// bit[22:16]  sub_snap_to_ref_mv_diff
// bit[15:4]   sub_glitch_mv_sad
// bit[3:0]    sub_glitch_mv_diff
#define HCODEC_ME_SUB_SNAP_GLITCH                  0x0f5e
// bit[31:20]  sad_act_limit
// bit[19:8]   s_a_any_sad
// bit[7]      Reserved
// bit[6:5]    sub_merge_method
// bit[4]      use_sub_act_result
// bit[3]      s_a_rnd
// bit[2]      Reserved
// bit[1]      sub_act_en_16
// bit[0]      sub_act_en
#define HCODEC_ME_SUB_ACT_CTL                      0x0f5f
//
// Closing file:  qdct_regs.h
//

#endif // DOS_CBUS_REGISTER_H

