#ifndef __MACH_MESSON_REG_ADDR_H
#define __MACH_MESSON_REG_ADDR_H
//CBUS REG ADDR
#include "registers.h"
#include "ao_reg.h"
#define P_SECOND_DEMUX_OFFSET_0 CBUS_REG_ADDR(SECOND_DEMUX_OFFSET_0)
#define P_THIRD_DEMUX_OFFSET_0 CBUS_REG_ADDR(THIRD_DEMUX_OFFSET_0)
#define P_STB_TOP_CONFIG CBUS_REG_ADDR(STB_TOP_CONFIG)
#define P_TS_TOP_CONFIG CBUS_REG_ADDR(TS_TOP_CONFIG)
#define P_TS_FILE_CONFIG CBUS_REG_ADDR(TS_FILE_CONFIG)
#define P_TS_PL_PID_INDEX CBUS_REG_ADDR(TS_PL_PID_INDEX)
#define P_TS_PL_PID_DATA CBUS_REG_ADDR(TS_PL_PID_DATA)
#define P_COMM_DESC_KEY0 CBUS_REG_ADDR(COMM_DESC_KEY0)
#define P_COMM_DESC_KEY1 CBUS_REG_ADDR(COMM_DESC_KEY1)
#define P_COMM_DESC_KEY_RW CBUS_REG_ADDR(COMM_DESC_KEY_RW)
#define P_PREG_CTLREG0_ADDR CBUS_REG_ADDR(PREG_CTLREG0_ADDR)
#define P_XIF_DUMMY_0 CBUS_REG_ADDR(XIF_DUMMY_0)
#define P_XIF_DUMMY_1 CBUS_REG_ADDR(XIF_DUMMY_1)
#define P_XIF_DUMMY_2 CBUS_REG_ADDR(XIF_DUMMY_2)
#define P_XIF_DUMMY_3 CBUS_REG_ADDR(XIF_DUMMY_3)
#define P_XIF_DUMMY_4 CBUS_REG_ADDR(XIF_DUMMY_4)
#define P_PREG_JTAG_GPIO_ADDR CBUS_REG_ADDR(PREG_JTAG_GPIO_ADDR)
#define P_PREG_EGPIO_EN_N CBUS_REG_ADDR(PREG_EGPIO_EN_N)
#define P_PREG_EGPIO_O CBUS_REG_ADDR(PREG_EGPIO_O)
#define P_PREG_EGPIO_I CBUS_REG_ADDR(PREG_EGPIO_I)
#define P_PREG_FGPIO_EN_N CBUS_REG_ADDR(PREG_FGPIO_EN_N)
#define P_PREG_FGPIO_O CBUS_REG_ADDR(PREG_FGPIO_O)
#define P_PREG_FGPIO_I CBUS_REG_ADDR(PREG_FGPIO_I)
#define P_PREG_GGPIO_EN_N CBUS_REG_ADDR(PREG_GGPIO_EN_N)
#define P_PREG_GGPIO_O CBUS_REG_ADDR(PREG_GGPIO_O)
#define P_PREG_GGPIO_I CBUS_REG_ADDR(PREG_GGPIO_I)
#define P_PREG_HGPIO_EN_N CBUS_REG_ADDR(PREG_HGPIO_EN_N)
#define P_PREG_HGPIO_O CBUS_REG_ADDR(PREG_HGPIO_O)
#define P_PREG_HGPIO_I CBUS_REG_ADDR(PREG_HGPIO_I)
#define P_PREG_PAD_GPIO0_EN_N CBUS_REG_ADDR(PREG_PAD_GPIO0_EN_N)
#define P_PREG_PAD_GPIO0_O CBUS_REG_ADDR(PREG_PAD_GPIO0_O)
#define P_PREG_PAD_GPIO0_I CBUS_REG_ADDR(PREG_PAD_GPIO0_I)
#define P_PREG_PAD_GPIO1_EN_N CBUS_REG_ADDR(PREG_PAD_GPIO1_EN_N)
#define P_PREG_PAD_GPIO1_O CBUS_REG_ADDR(PREG_PAD_GPIO1_O)
#define P_PREG_PAD_GPIO1_I CBUS_REG_ADDR(PREG_PAD_GPIO1_I)
#define P_PREG_PAD_GPIO2_EN_N CBUS_REG_ADDR(PREG_PAD_GPIO2_EN_N)
#define P_PREG_PAD_GPIO2_O CBUS_REG_ADDR(PREG_PAD_GPIO2_O)
#define P_PREG_PAD_GPIO2_I CBUS_REG_ADDR(PREG_PAD_GPIO2_I)
#define P_PREG_PAD_GPIO3_EN_N CBUS_REG_ADDR(PREG_PAD_GPIO3_EN_N)
#define P_PREG_PAD_GPIO3_O CBUS_REG_ADDR(PREG_PAD_GPIO3_O)
#define P_PREG_PAD_GPIO3_I CBUS_REG_ADDR(PREG_PAD_GPIO3_I)
#define P_PREG_PAD_GPIO4_EN_N CBUS_REG_ADDR(PREG_PAD_GPIO4_EN_N)
#define P_PREG_PAD_GPIO4_O CBUS_REG_ADDR(PREG_PAD_GPIO4_O)
#define P_PREG_PAD_GPIO4_I CBUS_REG_ADDR(PREG_PAD_GPIO4_I)
#define P_PREG_PAD_GPIO5_EN_N CBUS_REG_ADDR(PREG_PAD_GPIO5_EN_N)
#define P_PREG_PAD_GPIO5_O CBUS_REG_ADDR(PREG_PAD_GPIO5_O)
#define P_PREG_PAD_GPIO5_I CBUS_REG_ADDR(PREG_PAD_GPIO5_I)
#define P_A9_CFG0 CBUS_REG_ADDR(A9_CFG0)
#define P_A9_CFG1 CBUS_REG_ADDR(A9_CFG1)
#define P_A9_CFG2 CBUS_REG_ADDR(A9_CFG2)
#define P_A9_PERIPH_BASE CBUS_REG_ADDR(A9_PERIPH_BASE)
#define P_A9_L2_REG_BASE CBUS_REG_ADDR(A9_L2_REG_BASE)
#define P_A9_L2_STATUS CBUS_REG_ADDR(A9_L2_STATUS)
#define P_A9_POR_CFG CBUS_REG_ADDR(A9_POR_CFG)
#define P_PERIPHS_PIN_MUX_0 CBUS_REG_ADDR(PERIPHS_PIN_MUX_0)
#define P_PERIPHS_PIN_MUX_1 CBUS_REG_ADDR(PERIPHS_PIN_MUX_1)
#define P_PERIPHS_PIN_MUX_2 CBUS_REG_ADDR(PERIPHS_PIN_MUX_2)
#define P_PERIPHS_PIN_MUX_3 CBUS_REG_ADDR(PERIPHS_PIN_MUX_3)
#define P_PERIPHS_PIN_MUX_4 CBUS_REG_ADDR(PERIPHS_PIN_MUX_4)
#define P_PERIPHS_PIN_MUX_5 CBUS_REG_ADDR(PERIPHS_PIN_MUX_5)
#define P_PERIPHS_PIN_MUX_6 CBUS_REG_ADDR(PERIPHS_PIN_MUX_6)
#define P_PERIPHS_PIN_MUX_7 CBUS_REG_ADDR(PERIPHS_PIN_MUX_7)
#define P_PERIPHS_PIN_MUX_8 CBUS_REG_ADDR(PERIPHS_PIN_MUX_8)
#define P_PERIPHS_PIN_MUX_9 CBUS_REG_ADDR(PERIPHS_PIN_MUX_9)
#define P_PERIPHS_PIN_MUX_10 CBUS_REG_ADDR(PERIPHS_PIN_MUX_10)
#define P_PERIPHS_PIN_MUX_11 CBUS_REG_ADDR(PERIPHS_PIN_MUX_11)
#define P_PERIPHS_PIN_MUX_12 CBUS_REG_ADDR(PERIPHS_PIN_MUX_12)
#define P_PAD_PULL_UP_REG0 CBUS_REG_ADDR(PAD_PULL_UP_REG0)
#define P_PAD_PULL_UP_REG1 CBUS_REG_ADDR(PAD_PULL_UP_REG1)
#define P_PAD_PULL_UP_REG2 CBUS_REG_ADDR(PAD_PULL_UP_REG2)
#define P_PAD_PULL_UP_REG3 CBUS_REG_ADDR(PAD_PULL_UP_REG3)
#define P_RAND64_ADDR0 CBUS_REG_ADDR(RAND64_ADDR0)
#define P_RAND64_ADDR1 CBUS_REG_ADDR(RAND64_ADDR1)
#define P_PREG_ETHERNET_ADDR0 CBUS_REG_ADDR(PREG_ETHERNET_ADDR0)
#define P_PREG_AM_ANALOG_ADDR CBUS_REG_ADDR(PREG_AM_ANALOG_ADDR)
#define P_PREG_MALI_BYTE_CNTL CBUS_REG_ADDR(PREG_MALI_BYTE_CNTL)
#define P_PREG_WIFI_CNTL CBUS_REG_ADDR(PREG_WIFI_CNTL)
#define P_PREG_SATA_REG0 CBUS_REG_ADDR(PREG_SATA_REG0)
#define P_PREG_SATA_REG1 CBUS_REG_ADDR(PREG_SATA_REG1)
#define P_PREG_SATA_REG2 CBUS_REG_ADDR(PREG_SATA_REG2)
#define P_PREG_SATA_REG3 CBUS_REG_ADDR(PREG_SATA_REG3)
#define P_PREG_SATA_REG4 CBUS_REG_ADDR(PREG_SATA_REG4)
#define P_PREG_SATA_REG5 CBUS_REG_ADDR(PREG_SATA_REG5)
#define P_AM_ANALOG_TOP_REG0 CBUS_REG_ADDR(AM_ANALOG_TOP_REG0)
#define P_PREG_STICKY_REG0 CBUS_REG_ADDR(PREG_STICKY_REG0)
#define P_PREG_STICKY_REG1 CBUS_REG_ADDR(PREG_STICKY_REG1)
#define P_AM_RING_OSC_REG0 CBUS_REG_ADDR(AM_RING_OSC_REG0)
#define P_USB_ADDR0 CBUS_REG_ADDR(USB_ADDR0)
#define P_USB_ADDR1 CBUS_REG_ADDR(USB_ADDR1)
#define P_USB_ADDR2 CBUS_REG_ADDR(USB_ADDR2)
#define P_USB_ADDR3 CBUS_REG_ADDR(USB_ADDR3)
#define P_USB_ADDR4 CBUS_REG_ADDR(USB_ADDR4)
#define P_USB_ADDR5 CBUS_REG_ADDR(USB_ADDR5)
#define P_USB_ADDR6 CBUS_REG_ADDR(USB_ADDR6)
#define P_SMARTCARD_REG0 CBUS_REG_ADDR(SMARTCARD_REG0)
#define P_SMARTCARD_REG1 CBUS_REG_ADDR(SMARTCARD_REG1)
#define P_SMARTCARD_REG2 CBUS_REG_ADDR(SMARTCARD_REG2)
#define P_SMARTCARD_STATUS CBUS_REG_ADDR(SMARTCARD_STATUS)
#define P_SMARTCARD_INTR CBUS_REG_ADDR(SMARTCARD_INTR)
#define P_SMARTCARD_REG5 CBUS_REG_ADDR(SMARTCARD_REG5)
#define P_SMARTCARD_REG6 CBUS_REG_ADDR(SMARTCARD_REG6)
#define P_SMARTCARD_FIFO CBUS_REG_ADDR(SMARTCARD_FIFO)
#define P_IR_DEC_LDR_ACTIVE CBUS_REG_ADDR(IR_DEC_LDR_ACTIVE)
#define P_IR_DEC_LDR_IDLE CBUS_REG_ADDR(IR_DEC_LDR_IDLE)
#define P_IR_DEC_LDR_REPEAT CBUS_REG_ADDR(IR_DEC_LDR_REPEAT)
#define P_IR_DEC_BIT_0 CBUS_REG_ADDR(IR_DEC_BIT_0)
#define P_IR_DEC_REG0 CBUS_REG_ADDR(IR_DEC_REG0)
#define P_IR_DEC_FRAME CBUS_REG_ADDR(IR_DEC_FRAME)
#define P_IR_DEC_STATUS CBUS_REG_ADDR(IR_DEC_STATUS)
#define P_IR_DEC_REG1 CBUS_REG_ADDR(IR_DEC_REG1)
#define P_WIFI_ADC_SAMPLING CBUS_REG_ADDR(WIFI_ADC_SAMPLING)
#define P_WIFI_ADC_READBACK CBUS_REG_ADDR(WIFI_ADC_READBACK)
#define P_UART0_WFIFO CBUS_REG_ADDR(UART0_WFIFO)
#define P_UART0_RFIFO CBUS_REG_ADDR(UART0_RFIFO)
#define P_UART0_CONTROL CBUS_REG_ADDR(UART0_CONTROL)
#define P_UART0_STATUS CBUS_REG_ADDR(UART0_STATUS)
#define P_UART0_MISC CBUS_REG_ADDR(UART0_MISC)
#define P_UART1_WFIFO CBUS_REG_ADDR(UART1_WFIFO)
#define P_UART1_RFIFO CBUS_REG_ADDR(UART1_RFIFO)
#define P_UART1_CONTROL CBUS_REG_ADDR(UART1_CONTROL)
#define P_UART1_STATUS CBUS_REG_ADDR(UART1_STATUS)
#define P_UART1_MISC CBUS_REG_ADDR(UART1_MISC)
#define P_DYNAMIC_PIN_SAMPLE_REG0 CBUS_REG_ADDR(DYNAMIC_PIN_SAMPLE_REG0)
#define P_DYNAMIC_PIN_SAMPLE_REG1 CBUS_REG_ADDR(DYNAMIC_PIN_SAMPLE_REG1)
#define P_I2C_M_0_CONTROL_REG CBUS_REG_ADDR(I2C_M_0_CONTROL_REG)
#define P_I2C_M_MANUAL_SDA_I CBUS_REG_ADDR(I2C_M_MANUAL_SDA_I)
#define P_I2C_M_MANUAL_SCL_I CBUS_REG_ADDR(I2C_M_MANUAL_SCL_I)
#define P_I2C_M_MANUAL_SDA_O CBUS_REG_ADDR(I2C_M_MANUAL_SDA_O)
#define P_I2C_M_MANUAL_SCL_O CBUS_REG_ADDR(I2C_M_MANUAL_SCL_O)
#define P_I2C_M_MANUAL_EN CBUS_REG_ADDR(I2C_M_MANUAL_EN)
#define P_I2C_M_DELAY_MSB CBUS_REG_ADDR(I2C_M_DELAY_MSB)
#define P_I2C_M_DELAY_LSB CBUS_REG_ADDR(I2C_M_DELAY_LSB)
#define P_I2C_M_DATA_CNT_MSB CBUS_REG_ADDR(I2C_M_DATA_CNT_MSB)
#define P_I2C_M_DATA_CNT_LSB CBUS_REG_ADDR(I2C_M_DATA_CNT_LSB)
#define P_I2C_M_CURR_TOKEN_MSB CBUS_REG_ADDR(I2C_M_CURR_TOKEN_MSB)
#define P_I2C_M_CURR_TOKEN_LSB CBUS_REG_ADDR(I2C_M_CURR_TOKEN_LSB)
#define P_I2C_M_ERROR CBUS_REG_ADDR(I2C_M_ERROR)
#define P_I2C_M_STATUS CBUS_REG_ADDR(I2C_M_STATUS)
#define P_I2C_M_ACK_IGNORE CBUS_REG_ADDR(I2C_M_ACK_IGNORE)
#define P_I2C_M_START CBUS_REG_ADDR(I2C_M_START)
#define P_I2C_M_0_SLAVE_ADDR CBUS_REG_ADDR(I2C_M_0_SLAVE_ADDR)
#define P_I2C_M_0_TOKEN_LIST0 CBUS_REG_ADDR(I2C_M_0_TOKEN_LIST0)
#define P_I2C_M_0_TOKEN_LIST1 CBUS_REG_ADDR(I2C_M_0_TOKEN_LIST1)
#define P_I2C_M_0_WDATA_REG0 CBUS_REG_ADDR(I2C_M_0_WDATA_REG0)
#define P_I2C_M_0_WDATA_REG1 CBUS_REG_ADDR(I2C_M_0_WDATA_REG1)
#define P_I2C_M_0_RDATA_REG0 CBUS_REG_ADDR(I2C_M_0_RDATA_REG0)
#define P_I2C_M_0_RDATA_REG1 CBUS_REG_ADDR(I2C_M_0_RDATA_REG1)
#define P_I2C_M_1_CONTROL_REG CBUS_REG_ADDR(I2C_M_1_CONTROL_REG)
#define P_I2C_M_1_SLAVE_ADDR CBUS_REG_ADDR(I2C_M_1_SLAVE_ADDR)
#define P_I2C_M_1_TOKEN_LIST0 CBUS_REG_ADDR(I2C_M_1_TOKEN_LIST0)
#define P_I2C_M_1_TOKEN_LIST1 CBUS_REG_ADDR(I2C_M_1_TOKEN_LIST1)
#define P_I2C_M_1_WDATA_REG0 CBUS_REG_ADDR(I2C_M_1_WDATA_REG0)
#define P_I2C_M_1_WDATA_REG1 CBUS_REG_ADDR(I2C_M_1_WDATA_REG1)
#define P_I2C_M_1_RDATA_REG0 CBUS_REG_ADDR(I2C_M_1_RDATA_REG0)
#define P_I2C_M_1_RDATA_REG1 CBUS_REG_ADDR(I2C_M_1_RDATA_REG1)
#define P_I2C_S_CONTROL_REG CBUS_REG_ADDR(I2C_S_CONTROL_REG)
#define P_I2C_S_SEND_REG CBUS_REG_ADDR(I2C_S_SEND_REG)
#define P_I2C_S_RECV_REG CBUS_REG_ADDR(I2C_S_RECV_REG)
#define P_I2C_S_CNTL1_REG CBUS_REG_ADDR(I2C_S_CNTL1_REG)
#define P_PWM_PWM_A CBUS_REG_ADDR(PWM_PWM_A)
#define P_PWM_PWM_B CBUS_REG_ADDR(PWM_PWM_B)
#define P_PWM_MISC_REG_AB CBUS_REG_ADDR(PWM_MISC_REG_AB)
#define P_PWM_DELTA_SIGMA_AB CBUS_REG_ADDR(PWM_DELTA_SIGMA_AB)
#define P_EFUSE_CNTL0 CBUS_REG_ADDR(EFUSE_CNTL0)
#define P_EFUSE_CNTL1 CBUS_REG_ADDR(EFUSE_CNTL1)
#define P_EFUSE_CNTL2 CBUS_REG_ADDR(EFUSE_CNTL2)
#define P_EFUSE_CNTL3 CBUS_REG_ADDR(EFUSE_CNTL3)
#define P_EFUSE_CNTL4 CBUS_REG_ADDR(EFUSE_CNTL4)
#define P_ATAPI_IDEREG0 CBUS_REG_ADDR(ATAPI_IDEREG0)
#define P_IDE_UDMA_PIO_STATE CBUS_REG_ADDR(IDE_UDMA_PIO_STATE)
#define P_IDE_BUSY CBUS_REG_ADDR(IDE_BUSY)
#define P_IDE_ERROR_BIT CBUS_REG_ADDR(IDE_ERROR_BIT)
#define P_IDE_DMARQ_BIT CBUS_REG_ADDR(IDE_DMARQ_BIT)
#define P_IDE_IORDY_BIT CBUS_REG_ADDR(IDE_IORDY_BIT)
#define P_IDE_IORDY_EN_BIT CBUS_REG_ADDR(IDE_IORDY_EN_BIT)
#define P_IDE_DIS_CSEL_BIT CBUS_REG_ADDR(IDE_DIS_CSEL_BIT)
#define P_IDE_CSEL_BIT CBUS_REG_ADDR(IDE_CSEL_BIT)
#define P_IDE_IRQ14 CBUS_REG_ADDR(IDE_IRQ14)
#define P_IDE_ATAPI_GPIO_EN CBUS_REG_ADDR(IDE_ATAPI_GPIO_EN)
#define P_IDE_DMARQ_FULL CBUS_REG_ADDR(IDE_DMARQ_FULL)
#define P_IDE_ENABLE CBUS_REG_ADDR(IDE_ENABLE)
#define P_ATAPI_IDEREG1 CBUS_REG_ADDR(ATAPI_IDEREG1)
#define P_ATAPI_IDEREG2 CBUS_REG_ADDR(ATAPI_IDEREG2)
#define P_IDE_XFER_CNT_MSB_BIT CBUS_REG_ADDR(IDE_XFER_CNT_MSB_BIT)
#define P_IDE_XFER_CNT_LSB_BIT CBUS_REG_ADDR(IDE_XFER_CNT_LSB_BIT)
#define P_ATAPI_CYCTIME CBUS_REG_ADDR(ATAPI_CYCTIME)
#define P_ATAPI_IDETIME CBUS_REG_ADDR(ATAPI_IDETIME)
#define P_ATAPI_PIO_TIMING CBUS_REG_ADDR(ATAPI_PIO_TIMING)
#define P_ATAPI_TABLE_ADD_REG CBUS_REG_ADDR(ATAPI_TABLE_ADD_REG)
#define P_ATAPI_IDEREG3 CBUS_REG_ADDR(ATAPI_IDEREG3)
#define P_ATAPI_UDMA_REG0 CBUS_REG_ADDR(ATAPI_UDMA_REG0)
#define P_ATAPI_UDMA_REG1 CBUS_REG_ADDR(ATAPI_UDMA_REG1)
#define P_TRANS_PWMA_REG0 CBUS_REG_ADDR(TRANS_PWMA_REG0)
#define P_TRANS_PWMA_REG1 CBUS_REG_ADDR(TRANS_PWMA_REG1)
#define P_TRANS_PWMA_MUX0 CBUS_REG_ADDR(TRANS_PWMA_MUX0)
#define P_TRANS_PWMA_MUX1 CBUS_REG_ADDR(TRANS_PWMA_MUX1)
#define P_TRANS_PWMA_MUX2 CBUS_REG_ADDR(TRANS_PWMA_MUX2)
#define P_TRANS_PWMA_MUX3 CBUS_REG_ADDR(TRANS_PWMA_MUX3)
#define P_TRANS_PWMA_MUX4 CBUS_REG_ADDR(TRANS_PWMA_MUX4)
#define P_TRANS_PWMA_MUX5 CBUS_REG_ADDR(TRANS_PWMA_MUX5)
#define P_TRANS_PWMB_REG0 CBUS_REG_ADDR(TRANS_PWMB_REG0)
#define P_TRANS_PWMB_REG1 CBUS_REG_ADDR(TRANS_PWMB_REG1)
#define P_TRANS_PWMB_MUX0 CBUS_REG_ADDR(TRANS_PWMB_MUX0)
#define P_TRANS_PWMB_MUX1 CBUS_REG_ADDR(TRANS_PWMB_MUX1)
#define P_TRANS_PWMB_MUX2 CBUS_REG_ADDR(TRANS_PWMB_MUX2)
#define P_TRANS_PWMB_MUX3 CBUS_REG_ADDR(TRANS_PWMB_MUX3)
#define P_TRANS_PWMB_MUX4 CBUS_REG_ADDR(TRANS_PWMB_MUX4)
#define P_TRANS_PWMB_MUX5 CBUS_REG_ADDR(TRANS_PWMB_MUX5)
#define P_PWM_PWM_C CBUS_REG_ADDR(PWM_PWM_C)
#define P_PWM_PWM_D CBUS_REG_ADDR(PWM_PWM_D)
#define P_PWM_MISC_REG_CD CBUS_REG_ADDR(PWM_MISC_REG_CD)
#define P_PWM_DELTA_SIGMA_CD CBUS_REG_ADDR(PWM_DELTA_SIGMA_CD)
#define P_SAR_ADC_REG0 CBUS_REG_ADDR(SAR_ADC_REG0)
#define P_SAR_ADC_CHAN_LIST CBUS_REG_ADDR(SAR_ADC_CHAN_LIST)
#define P_SAR_ADC_AVG_CNTL CBUS_REG_ADDR(SAR_ADC_AVG_CNTL)
#define P_SAR_ADC_REG3 CBUS_REG_ADDR(SAR_ADC_REG3)
#define P_SAR_ADC_DELAY CBUS_REG_ADDR(SAR_ADC_DELAY)
#define P_SAR_ADC_LAST_RD CBUS_REG_ADDR(SAR_ADC_LAST_RD)
#define P_SAR_ADC_FIFO_RD CBUS_REG_ADDR(SAR_ADC_FIFO_RD)
#define P_SAR_ADC_AUX_SW CBUS_REG_ADDR(SAR_ADC_AUX_SW)
#define P_SAR_ADC_CHAN_10_SW CBUS_REG_ADDR(SAR_ADC_CHAN_10_SW)
#define P_SAR_ADC_DETECT_IDLE_SW CBUS_REG_ADDR(SAR_ADC_DETECT_IDLE_SW)
#define P_SAR_ADC_DELTA_10 CBUS_REG_ADDR(SAR_ADC_DELTA_10)
#define P_CTOUCH_REG0 CBUS_REG_ADDR(CTOUCH_REG0)
#define P_CTOUCH_REG1 CBUS_REG_ADDR(CTOUCH_REG1)
#define P_CTOUCH_FIFO CBUS_REG_ADDR(CTOUCH_FIFO)
#define P_CTOUCH_REG3 CBUS_REG_ADDR(CTOUCH_REG3)
#define P_CTOUCH_INIT_CLK0 CBUS_REG_ADDR(CTOUCH_INIT_CLK0)
#define P_CTOUCH_INIT_CLK1 CBUS_REG_ADDR(CTOUCH_INIT_CLK1)
#define P_CTOUCH_REG6 CBUS_REG_ADDR(CTOUCH_REG6)
#define P_CTOUCH_GND_SW_MASK CBUS_REG_ADDR(CTOUCH_GND_SW_MASK)
#define P_CTOUCH_MSR_TB_SEL CBUS_REG_ADDR(CTOUCH_MSR_TB_SEL)
#define P_CTOUCH_CAP_THRESH0 CBUS_REG_ADDR(CTOUCH_CAP_THRESH0)
#define P_CTOUCH_CAP_THRESH1 CBUS_REG_ADDR(CTOUCH_CAP_THRESH1)
#define P_CTOUCH_CHAN_LIST0 CBUS_REG_ADDR(CTOUCH_CHAN_LIST0)
#define P_CTOUCH_CHAN_LIST1 CBUS_REG_ADDR(CTOUCH_CHAN_LIST1)
#define P_CTOUCH_MSR_TB0 CBUS_REG_ADDR(CTOUCH_MSR_TB0)
#define P_CTOUCH_MSR_TB1 CBUS_REG_ADDR(CTOUCH_MSR_TB1)
#define P_CTOUCH_REG15 CBUS_REG_ADDR(CTOUCH_REG15)
//#define P_RTC_ADDR0 CBUS_REG_ADDR(RTC_ADDR0)
//#define P_RTC_ADDR1 CBUS_REG_ADDR(RTC_ADDR1)
//#define P_RTC_ADDR2 CBUS_REG_ADDR(RTC_ADDR2)
//#define P_RTC_ADDR3 CBUS_REG_ADDR(RTC_ADDR3)
//#define P_RTC_ADDR4 CBUS_REG_ADDR(RTC_ADDR4)
#define P_MSR_CLK_REG0 CBUS_REG_ADDR(MSR_CLK_REG0)
#define P_MSR_CLK_REG1 CBUS_REG_ADDR(MSR_CLK_REG1)
#define P_MSR_CLK_REG2 CBUS_REG_ADDR(MSR_CLK_REG2)
#define P_LED_PWM_REG0 CBUS_REG_ADDR(LED_PWM_REG0)
#define P_LED_PWM_REG1 CBUS_REG_ADDR(LED_PWM_REG1)
#define P_LED_PWM_REG2 CBUS_REG_ADDR(LED_PWM_REG2)
#define P_LED_PWM_REG3 CBUS_REG_ADDR(LED_PWM_REG3)
#define P_LED_PWM_REG4 CBUS_REG_ADDR(LED_PWM_REG4)
#define P_VGHL_PWM_REG0 CBUS_REG_ADDR(VGHL_PWM_REG0)
#define P_VGHL_PWM_REG1 CBUS_REG_ADDR(VGHL_PWM_REG1)
#define P_VGHL_PWM_REG2 CBUS_REG_ADDR(VGHL_PWM_REG2)
#define P_VGHL_PWM_REG3 CBUS_REG_ADDR(VGHL_PWM_REG3)
#define P_VGHL_PWM_REG4 CBUS_REG_ADDR(VGHL_PWM_REG4)
#define P_AUDIN_SPDIF_MODE CBUS_REG_ADDR(AUDIN_SPDIF_MODE)
#define P_SPDIF_EN CBUS_REG_ADDR(SPDIF_EN)
#define P_SPDIF_IRQ_ITV CBUS_REG_ADDR(SPDIF_IRQ_ITV)
#define P_SPDIF_TIE_0 CBUS_REG_ADDR(SPDIF_TIE_0)
#define P_SPDIF_BIT_ORDER CBUS_REG_ADDR(SPDIF_BIT_ORDER)
#define P_SPDIF_CHNL_ORDER CBUS_REG_ADDR(SPDIF_CHNL_ORDER)
#define P_SPDIF_DATA_TYPE_SEL CBUS_REG_ADDR(SPDIF_DATA_TYPE_SEL)
#define P_SPDIF_PATH_SEL CBUS_REG_ADDR(SPDIF_PATH_SEL)
#define P_SPDIF_XTDCLK_UPD_ITVL CBUS_REG_ADDR(SPDIF_XTDCLK_UPD_ITVL)
#define P_SPDIF_CLKNUM_54U CBUS_REG_ADDR(SPDIF_CLKNUM_54U)
#define P_AUDIN_SPDIF_FS_CLK_RLTN CBUS_REG_ADDR(AUDIN_SPDIF_FS_CLK_RLTN)
#define P_SPDIF_CLKNUM_192K CBUS_REG_ADDR(SPDIF_CLKNUM_192K)
#define P_SPDIF_CLKNUM_96K CBUS_REG_ADDR(SPDIF_CLKNUM_96K)
#define P_SPDIF_CLKNUM_48K CBUS_REG_ADDR(SPDIF_CLKNUM_48K)
#define P_SPDIF_CLKNUM_44K CBUS_REG_ADDR(SPDIF_CLKNUM_44K)
#define P_SPDIF_CLKNUM_32K CBUS_REG_ADDR(SPDIF_CLKNUM_32K)
#define P_AUDIN_SPDIF_CHNL_STS_A CBUS_REG_ADDR(AUDIN_SPDIF_CHNL_STS_A)
#define P_AUDIN_SPDIF_CHNL_STS_B CBUS_REG_ADDR(AUDIN_SPDIF_CHNL_STS_B)
#define P_AUDIN_SPDIF_MISC CBUS_REG_ADDR(AUDIN_SPDIF_MISC)
#define P_AUDIN_SPDIF_NPCM_PCPD CBUS_REG_ADDR(AUDIN_SPDIF_NPCM_PCPD)
#define P_AUDIN_SPDIF_END CBUS_REG_ADDR(AUDIN_SPDIF_END)
#define P_AUDIN_I2SIN_CTRL CBUS_REG_ADDR(AUDIN_I2SIN_CTRL)
#define P_I2SIN_DIR CBUS_REG_ADDR(I2SIN_DIR)
#define P_I2SIN_CLK_SEL CBUS_REG_ADDR(I2SIN_CLK_SEL)
#define P_I2SIN_LRCLK_SEL CBUS_REG_ADDR(I2SIN_LRCLK_SEL)
#define P_I2SIN_POS_SYNC CBUS_REG_ADDR(I2SIN_POS_SYNC)
#define P_I2SIN_LRCLK_SKEW CBUS_REG_ADDR(I2SIN_LRCLK_SKEW)
#define P_I2SIN_LRCLK_INVT CBUS_REG_ADDR(I2SIN_LRCLK_INVT)
#define P_I2SIN_SIZE CBUS_REG_ADDR(I2SIN_SIZE)
#define P_I2SIN_CHAN_EN CBUS_REG_ADDR(I2SIN_CHAN_EN)
#define P_I2SIN_EN CBUS_REG_ADDR(I2SIN_EN)
#define P_AUDIN_I2S_END CBUS_REG_ADDR(AUDIN_I2S_END)
#define P_AUDIN_FIFO0_START CBUS_REG_ADDR(AUDIN_FIFO0_START)
#define P_AUDIN_FIFO0_END CBUS_REG_ADDR(AUDIN_FIFO0_END)
#define P_AUDIN_FIFO0_PTR CBUS_REG_ADDR(AUDIN_FIFO0_PTR)
#define P_AUDIN_FIFO0_INTR CBUS_REG_ADDR(AUDIN_FIFO0_INTR)
#define P_AUDIN_FIFO0_RDPTR CBUS_REG_ADDR(AUDIN_FIFO0_RDPTR)
#define P_AUDIN_FIFO0_CTRL CBUS_REG_ADDR(AUDIN_FIFO0_CTRL)
#define P_AUDIN_FIFO0_EN CBUS_REG_ADDR(AUDIN_FIFO0_EN)
#define P_AUDIN_FIFO0_RST CBUS_REG_ADDR(AUDIN_FIFO0_RST)
#define P_AUDIN_FIFO0_LOAD CBUS_REG_ADDR(AUDIN_FIFO0_LOAD)
#define P_AUDIN_FIFO0_DIN_SEL CBUS_REG_ADDR(AUDIN_FIFO0_DIN_SEL)
#define P_AUDIN_FIFO0_D32b CBUS_REG_ADDR(AUDIN_FIFO0_D32b)
#define P_AUDIN_FIFO0_h24b CBUS_REG_ADDR(AUDIN_FIFO0_h24b)
#define P_AUDIN_FIFO0_ENDIAN CBUS_REG_ADDR(AUDIN_FIFO0_ENDIAN)
#define P_AUDIN_FIFO0_CHAN CBUS_REG_ADDR(AUDIN_FIFO0_CHAN)
#define P_AUDIN_FIFO0_UG CBUS_REG_ADDR(AUDIN_FIFO0_UG)
#define P_AUDIN_FIFO0_DEST CBUS_REG_ADDR(AUDIN_FIFO0_DEST)
#define P_AUDIN_FIFO0_OV_MASK CBUS_REG_ADDR(AUDIN_FIFO0_OV_MASK)
#define P_AUDIN_FIFO0_INT_MASK CBUS_REG_ADDR(AUDIN_FIFO0_INT_MASK)
#define P_AUDIN_FIFO0_HOLD0_EN CBUS_REG_ADDR(AUDIN_FIFO0_HOLD0_EN)
#define P_AUDIN_FIFO0_HOLD1_EN CBUS_REG_ADDR(AUDIN_FIFO0_HOLD1_EN)
#define P_AUDIN_FIFO0_HOLD2_EN CBUS_REG_ADDR(AUDIN_FIFO0_HOLD2_EN)
#define P_AUDIN_FIFO0_HOLD0_SEL CBUS_REG_ADDR(AUDIN_FIFO0_HOLD0_SEL)
#define P_AUDIN_FIFO0_HOLD1_SEL CBUS_REG_ADDR(AUDIN_FIFO0_HOLD1_SEL)
#define P_AUDIN_FIFO0_HOLD2_SEL CBUS_REG_ADDR(AUDIN_FIFO0_HOLD2_SEL)
#define P_AUDIN_FIFO0_HOLD_LVL CBUS_REG_ADDR(AUDIN_FIFO0_HOLD_LVL)
#define P_AUDIN_FIFO0_LVL0 CBUS_REG_ADDR(AUDIN_FIFO0_LVL0)
#define P_AUDIN_FIFO0_LVL1 CBUS_REG_ADDR(AUDIN_FIFO0_LVL1)
#define P_AUDIN_FIFO0_LVL2 CBUS_REG_ADDR(AUDIN_FIFO0_LVL2)
#define P_AUDIN_FIFO1_START CBUS_REG_ADDR(AUDIN_FIFO1_START)
#define P_AUDIN_FIFO1_END CBUS_REG_ADDR(AUDIN_FIFO1_END)
#define P_AUDIN_FIFO1_PTR CBUS_REG_ADDR(AUDIN_FIFO1_PTR)
#define P_AUDIN_FIFO1_INTR CBUS_REG_ADDR(AUDIN_FIFO1_INTR)
#define P_AUDIN_FIFO1_RDPTR CBUS_REG_ADDR(AUDIN_FIFO1_RDPTR)
#define P_AUDIN_FIFO1_CTRL CBUS_REG_ADDR(AUDIN_FIFO1_CTRL)
#define P_AUDIN_FIFO1_EN CBUS_REG_ADDR(AUDIN_FIFO1_EN)
#define P_AUDIN_FIFO1_RST CBUS_REG_ADDR(AUDIN_FIFO1_RST)
#define P_AUDIN_FIFO1_LOAD CBUS_REG_ADDR(AUDIN_FIFO1_LOAD)
#define P_AUDIN_FIFO1_DIN_SEL CBUS_REG_ADDR(AUDIN_FIFO1_DIN_SEL)
#define P_AUDIN_FIFO1_D32b CBUS_REG_ADDR(AUDIN_FIFO1_D32b)
#define P_AUDIN_FIFO1_h24b CBUS_REG_ADDR(AUDIN_FIFO1_h24b)
#define P_AUDIN_FIFO1_ENDIAN CBUS_REG_ADDR(AUDIN_FIFO1_ENDIAN)
#define P_AUDIN_FIFO1_CHAN CBUS_REG_ADDR(AUDIN_FIFO1_CHAN)
#define P_AUDIN_FIFO1_UG CBUS_REG_ADDR(AUDIN_FIFO1_UG)
#define P_AUDIN_FIFO1_DEST CBUS_REG_ADDR(AUDIN_FIFO1_DEST)
#define P_AUDIN_FIFO1_OV_MASK CBUS_REG_ADDR(AUDIN_FIFO1_OV_MASK)
#define P_AUDIN_FIFO1_INT_MASK CBUS_REG_ADDR(AUDIN_FIFO1_INT_MASK)
#define P_AUDIN_FIFO1_LVL0 CBUS_REG_ADDR(AUDIN_FIFO1_LVL0)
#define P_AUDIN_FIFO1_LVL1 CBUS_REG_ADDR(AUDIN_FIFO1_LVL1)
#define P_AUDIN_FIFO1_LVL2 CBUS_REG_ADDR(AUDIN_FIFO1_LVL2)
#define P_AUDIN_FIFO0_REQID CBUS_REG_ADDR(AUDIN_FIFO0_REQID)
#define P_AUDIN_FIFO1_REQID CBUS_REG_ADDR(AUDIN_FIFO1_REQID)
#define P_AUDIN_FIFO_INT CBUS_REG_ADDR(AUDIN_FIFO_INT)
#define P_AUDIN_ADDR_END CBUS_REG_ADDR(AUDIN_ADDR_END)
#define P_BT_CTRL CBUS_REG_ADDR(BT_CTRL)
#define P_BT_SOFT_RESET CBUS_REG_ADDR(BT_SOFT_RESET)
#define P_BT_JPEG_START CBUS_REG_ADDR(BT_JPEG_START)
#define P_BT_JPEG_IGNORE_BYTES CBUS_REG_ADDR(BT_JPEG_IGNORE_BYTES)
#define P_BT_JPEG_IGNORE_LAST CBUS_REG_ADDR(BT_JPEG_IGNORE_LAST)
#define P_BT_UPDATE_ST_SEL CBUS_REG_ADDR(BT_UPDATE_ST_SEL)
#define P_BT_COLOR_REPEAT CBUS_REG_ADDR(BT_COLOR_REPEAT)
#define P_BT_VIDEO_MODE CBUS_REG_ADDR(BT_VIDEO_MODE)
#define P_BT_AUTO_FMT CBUS_REG_ADDR(BT_AUTO_FMT)
#define P_BT_PROG_MODE CBUS_REG_ADDR(BT_PROG_MODE)
#define P_BT_JPEG_MODE CBUS_REG_ADDR(BT_JPEG_MODE)
#define P_BT_XCLK27_EN_BIT CBUS_REG_ADDR(BT_XCLK27_EN_BIT)
#define P_BT_FID_EN_BIT CBUS_REG_ADDR(BT_FID_EN_BIT)
#define P_BT_CLK27_SEL_BIT CBUS_REG_ADDR(BT_CLK27_SEL_BIT)
#define P_BT_CLK27_PHASE_BIT CBUS_REG_ADDR(BT_CLK27_PHASE_BIT)
#define P_BT_ACE_MODE_BIT CBUS_REG_ADDR(BT_ACE_MODE_BIT)
#define P_BT_SLICE_MODE_BIT CBUS_REG_ADDR(BT_SLICE_MODE_BIT)
#define P_BT_FMT_MODE_BIT CBUS_REG_ADDR(BT_FMT_MODE_BIT)
#define P_BT_REF_MODE_BIT CBUS_REG_ADDR(BT_REF_MODE_BIT)
#define P_BT_MODE_BIT CBUS_REG_ADDR(BT_MODE_BIT)
#define P_BT_EN_BIT CBUS_REG_ADDR(BT_EN_BIT)
#define P_BT_VBISTART CBUS_REG_ADDR(BT_VBISTART)
#define P_BT_VBIEND CBUS_REG_ADDR(BT_VBIEND)
#define P_BT_FIELDSADR CBUS_REG_ADDR(BT_FIELDSADR)
#define P_BT_LINECTRL CBUS_REG_ADDR(BT_LINECTRL)
#define P_BT_VIDEOSTART CBUS_REG_ADDR(BT_VIDEOSTART)
#define P_BT_VIDEOEND CBUS_REG_ADDR(BT_VIDEOEND)
#define P_BT_SLICELINE0 CBUS_REG_ADDR(BT_SLICELINE0)
#define P_BT_SLICELINE1 CBUS_REG_ADDR(BT_SLICELINE1)
#define P_BT_PORT_CTRL CBUS_REG_ADDR(BT_PORT_CTRL)
#define P_BT_HSYNC_PHASE CBUS_REG_ADDR(BT_HSYNC_PHASE)
#define P_BT_VSYNC_PHASE CBUS_REG_ADDR(BT_VSYNC_PHASE)
#define P_BT_HSYNC_PULSE CBUS_REG_ADDR(BT_HSYNC_PULSE)
#define P_BT_VSYNC_PULSE CBUS_REG_ADDR(BT_VSYNC_PULSE)
#define P_BT_FID_PHASE CBUS_REG_ADDR(BT_FID_PHASE)
#define P_BT_FID_HSVS CBUS_REG_ADDR(BT_FID_HSVS)
#define P_BT_IDQ_EN CBUS_REG_ADDR(BT_IDQ_EN)
#define P_BT_IDQ_PHASE CBUS_REG_ADDR(BT_IDQ_PHASE)
#define P_BT_D8B CBUS_REG_ADDR(BT_D8B)
#define P_BT_10BTO8B CBUS_REG_ADDR(BT_10BTO8B)
#define P_BT_FID_DELAY CBUS_REG_ADDR(BT_FID_DELAY)
#define P_BT_VSYNC_DELAY CBUS_REG_ADDR(BT_VSYNC_DELAY)
#define P_BT_HSYNC_DELAY CBUS_REG_ADDR(BT_HSYNC_DELAY)
#define P_BT_SWAP_CTRL CBUS_REG_ADDR(BT_SWAP_CTRL)
#define P_BT_ANCISADR CBUS_REG_ADDR(BT_ANCISADR)
#define P_BT_ANCIEADR CBUS_REG_ADDR(BT_ANCIEADR)
#define P_BT_AFIFO_CTRL CBUS_REG_ADDR(BT_AFIFO_CTRL)
#define P_BT_601_CTRL0 CBUS_REG_ADDR(BT_601_CTRL0)
#define P_BT_601_CTRL1 CBUS_REG_ADDR(BT_601_CTRL1)
#define P_BT_601_CTRL2 CBUS_REG_ADDR(BT_601_CTRL2)
#define P_BT_601_CTRL3 CBUS_REG_ADDR(BT_601_CTRL3)
#define P_BT_FIELD_LUMA CBUS_REG_ADDR(BT_FIELD_LUMA)
#define P_BT_RAW_CTRL CBUS_REG_ADDR(BT_RAW_CTRL)
#define P_BT_STATUS CBUS_REG_ADDR(BT_STATUS)
#define P_BT_INT_CTRL CBUS_REG_ADDR(BT_INT_CTRL)
#define P_BT_ANCI_STATUS CBUS_REG_ADDR(BT_ANCI_STATUS)
#define P_BT_VLINE_STATUS CBUS_REG_ADDR(BT_VLINE_STATUS)
#define P_BT_AFIFO_PTR CBUS_REG_ADDR(BT_AFIFO_PTR)
#define P_BT_JPEGBYTENUM CBUS_REG_ADDR(BT_JPEGBYTENUM)
#define P_BT_ERR_CNT CBUS_REG_ADDR(BT_ERR_CNT)
#define P_BT_JPEG_STATUS0 CBUS_REG_ADDR(BT_JPEG_STATUS0)
#define P_BT_JPEG_STATUS1 CBUS_REG_ADDR(BT_JPEG_STATUS1)
#define P_BT656_ADDR_END CBUS_REG_ADDR(BT656_ADDR_END)
#define P_NDMA_CNTL_REG0 CBUS_REG_ADDR(NDMA_CNTL_REG0)
#define P_NDMA_STATUS CBUS_REG_ADDR(NDMA_STATUS)
#define P_NDMA_PERIODIC_INT_DLY_MSB CBUS_REG_ADDR(NDMA_PERIODIC_INT_DLY_MSB)
#define P_NDMA_PERIODIC_INT_DLY_LSB CBUS_REG_ADDR(NDMA_PERIODIC_INT_DLY_LSB)
#define P_NDMA_PERIODIC_INT_EN CBUS_REG_ADDR(NDMA_PERIODIC_INT_EN)
#define P_NDMA_ENABLE CBUS_REG_ADDR(NDMA_ENABLE)
#define P_NDMA_AHB_DELAY_MSB CBUS_REG_ADDR(NDMA_AHB_DELAY_MSB)
#define P_NDMA_AHB_DELAY_LSB CBUS_REG_ADDR(NDMA_AHB_DELAY_LSB)
#define P_NDMA_TABLE_ADD_REG CBUS_REG_ADDR(NDMA_TABLE_ADD_REG)
#define P_NDMA_TDES_KEY_LO CBUS_REG_ADDR(NDMA_TDES_KEY_LO)
#define P_NDMA_TDES_KEY_HI CBUS_REG_ADDR(NDMA_TDES_KEY_HI)
#define P_NDMA_TDES_CONTROL CBUS_REG_ADDR(NDMA_TDES_CONTROL)
#define P_NDMA_AES_CONTROL CBUS_REG_ADDR(NDMA_AES_CONTROL)
#define P_NDMA_AES_RK_FIFO CBUS_REG_ADDR(NDMA_AES_RK_FIFO)
#define P_NDMA_CRC_OUT CBUS_REG_ADDR(NDMA_CRC_OUT)
#define P_NDMA_THREAD_REG CBUS_REG_ADDR(NDMA_THREAD_REG)
#define P_NDMA_THREAD_TABLE_START0 CBUS_REG_ADDR(NDMA_THREAD_TABLE_START0)
#define P_NDMA_THREAD_TABLE_CURR0 CBUS_REG_ADDR(NDMA_THREAD_TABLE_CURR0)
#define P_NDMA_THREAD_TABLE_END0 CBUS_REG_ADDR(NDMA_THREAD_TABLE_END0)
#define P_NDMA_THREAD_TABLE_START1 CBUS_REG_ADDR(NDMA_THREAD_TABLE_START1)
#define P_NDMA_THREAD_TABLE_CURR1 CBUS_REG_ADDR(NDMA_THREAD_TABLE_CURR1)
#define P_NDMA_THREAD_TABLE_END1 CBUS_REG_ADDR(NDMA_THREAD_TABLE_END1)
#define P_NDMA_THREAD_TABLE_START2 CBUS_REG_ADDR(NDMA_THREAD_TABLE_START2)
#define P_NDMA_THREAD_TABLE_CURR2 CBUS_REG_ADDR(NDMA_THREAD_TABLE_CURR2)
#define P_NDMA_THREAD_TABLE_END2 CBUS_REG_ADDR(NDMA_THREAD_TABLE_END2)
#define P_NDMA_THREAD_TABLE_START3 CBUS_REG_ADDR(NDMA_THREAD_TABLE_START3)
#define P_NDMA_THREAD_TABLE_CURR3 CBUS_REG_ADDR(NDMA_THREAD_TABLE_CURR3)
#define P_NDMA_THREAD_TABLE_END3 CBUS_REG_ADDR(NDMA_THREAD_TABLE_END3)
#define P_NDMA_CNTL_REG1 CBUS_REG_ADDR(NDMA_CNTL_REG1)
#define P_STREAM_EVENT_INFO CBUS_REG_ADDR(STREAM_EVENT_INFO)
#define P_STREAM_OUTPUT_CONFIG CBUS_REG_ADDR(STREAM_OUTPUT_CONFIG)
#define P_C_D_BUS_CONTROL CBUS_REG_ADDR(C_D_BUS_CONTROL)
#define P_C_DATA CBUS_REG_ADDR(C_DATA)
#define P_STREAM_BUS_CONFIG CBUS_REG_ADDR(STREAM_BUS_CONFIG)
#define P_STREAM_DATA_IN_CONFIG CBUS_REG_ADDR(STREAM_DATA_IN_CONFIG)
#define P_STREAM_WAIT_IRQ_CONFIG CBUS_REG_ADDR(STREAM_WAIT_IRQ_CONFIG)
#define P_STREAM_EVENT_CTL CBUS_REG_ADDR(STREAM_EVENT_CTL)
#define P_CMD_ARGUMENT CBUS_REG_ADDR(CMD_ARGUMENT)
#define P_CMD_SEND CBUS_REG_ADDR(CMD_SEND)
#define P_SDIO_CONFIG CBUS_REG_ADDR(SDIO_CONFIG)
#define P_SDIO_STATUS_IRQ CBUS_REG_ADDR(SDIO_STATUS_IRQ)
#define P_SDIO_IRQ_CONFIG CBUS_REG_ADDR(SDIO_IRQ_CONFIG)
#define P_SDIO_MULT_CONFIG CBUS_REG_ADDR(SDIO_MULT_CONFIG)
#define P_SDIO_M_ADDR CBUS_REG_ADDR(SDIO_M_ADDR)
#define P_SDIO_EXTENSION CBUS_REG_ADDR(SDIO_EXTENSION)
#define P_ASYNC_FIFO_REG0 CBUS_REG_ADDR(ASYNC_FIFO_REG0)
#define P_ASYNC_FIFO_REG1 CBUS_REG_ADDR(ASYNC_FIFO_REG1)
#define P_ASYNC_FIFO_FLUSH_STATUS CBUS_REG_ADDR(ASYNC_FIFO_FLUSH_STATUS)
#define P_ASYNC_FIFO_ERR CBUS_REG_ADDR(ASYNC_FIFO_ERR)
#define P_ASYNC_FIFO_FIFO_EMPTY CBUS_REG_ADDR(ASYNC_FIFO_FIFO_EMPTY)
#define P_ASYNC_FIFO_TO_HIU CBUS_REG_ADDR(ASYNC_FIFO_TO_HIU)
#define P_ASYNC_FIFO_FLUSH CBUS_REG_ADDR(ASYNC_FIFO_FLUSH)
#define P_ASYNC_FIFO_RESET CBUS_REG_ADDR(ASYNC_FIFO_RESET)
#define P_ASYNC_FIFO_WRAP_EN CBUS_REG_ADDR(ASYNC_FIFO_WRAP_EN)
#define P_ASYNC_FIFO_FLUSH_EN CBUS_REG_ADDR(ASYNC_FIFO_FLUSH_EN)
#define P_ASYNC_FIFO_RESIDUAL_MSB CBUS_REG_ADDR(ASYNC_FIFO_RESIDUAL_MSB)
#define P_ASYNC_FIFO_RESIDUAL_LSB CBUS_REG_ADDR(ASYNC_FIFO_RESIDUAL_LSB)
#define P_ASYNC_FIFO_FLUSH_CNT_MSB CBUS_REG_ADDR(ASYNC_FIFO_FLUSH_CNT_MSB)
#define P_ASYNC_FIFO_FLUSH_CNT_LSB CBUS_REG_ADDR(ASYNC_FIFO_FLUSH_CNT_LSB)
#define P_ASYNC_FIFO_REG2 CBUS_REG_ADDR(ASYNC_FIFO_REG2)
#define P_ASYNC_FIFO_FIFO_FULL CBUS_REG_ADDR(ASYNC_FIFO_FIFO_FULL)
#define P_ASYNC_FIFO_FILL_STATUS CBUS_REG_ADDR(ASYNC_FIFO_FILL_STATUS)
#define P_ASYNC_FIFO_SOURCE_MSB CBUS_REG_ADDR(ASYNC_FIFO_SOURCE_MSB)
#define P_ASYNC_FIFO_SOURCE_LSB CBUS_REG_ADDR(ASYNC_FIFO_SOURCE_LSB)
#define P_ASYNC_FIFO_ENDIAN_MSB CBUS_REG_ADDR(ASYNC_FIFO_ENDIAN_MSB)
#define P_ASYNC_FIFO_ENDIAN_LSB CBUS_REG_ADDR(ASYNC_FIFO_ENDIAN_LSB)
#define P_ASYNC_FIFO_FILL_EN CBUS_REG_ADDR(ASYNC_FIFO_FILL_EN)
#define P_ASYNC_FIFO_FILL_CNT_MSB CBUS_REG_ADDR(ASYNC_FIFO_FILL_CNT_MSB)
#define P_ASYNC_FIFO_FILL_CNT_LSB CBUS_REG_ADDR(ASYNC_FIFO_FILL_CNT_LSB)
#define P_ASYNC_FIFO_REG3 CBUS_REG_ADDR(ASYNC_FIFO_REG3)
#define P_ASYNC_FLUSH_SIZE_IRQ_MSB CBUS_REG_ADDR(ASYNC_FLUSH_SIZE_IRQ_MSB)
#define P_ASYNC_FLUSH_SIZE_IRQ_LSB CBUS_REG_ADDR(ASYNC_FLUSH_SIZE_IRQ_LSB)
#define P_ASYNC_FIFO2_REG0 CBUS_REG_ADDR(ASYNC_FIFO2_REG0)
#define P_ASYNC_FIFO2_REG1 CBUS_REG_ADDR(ASYNC_FIFO2_REG1)
#define P_ASYNC_FIFO2_REG2 CBUS_REG_ADDR(ASYNC_FIFO2_REG2)
#define P_ASYNC_FIFO2_REG3 CBUS_REG_ADDR(ASYNC_FIFO2_REG3)
#define P_SPI_FLASH_CMD CBUS_REG_ADDR(SPI_FLASH_CMD)
#define P_SPI_FLASH_READ CBUS_REG_ADDR(SPI_FLASH_READ)
#define P_SPI_FLASH_WREN CBUS_REG_ADDR(SPI_FLASH_WREN)
#define P_SPI_FLASH_WRDI CBUS_REG_ADDR(SPI_FLASH_WRDI)
#define P_SPI_FLASH_RDID CBUS_REG_ADDR(SPI_FLASH_RDID)
#define P_SPI_FLASH_RDSR CBUS_REG_ADDR(SPI_FLASH_RDSR)
#define P_SPI_FLASH_WRSR CBUS_REG_ADDR(SPI_FLASH_WRSR)
#define P_SPI_FLASH_PP CBUS_REG_ADDR(SPI_FLASH_PP)
#define P_SPI_FLASH_SE CBUS_REG_ADDR(SPI_FLASH_SE)
#define P_SPI_FLASH_BE CBUS_REG_ADDR(SPI_FLASH_BE)
#define P_SPI_FLASH_CE CBUS_REG_ADDR(SPI_FLASH_CE)
#define P_SPI_FLASH_DP CBUS_REG_ADDR(SPI_FLASH_DP)
#define P_SPI_FLASH_RES CBUS_REG_ADDR(SPI_FLASH_RES)
#define P_SPI_HPM CBUS_REG_ADDR(SPI_HPM)
#define P_SPI_FLASH_USR CBUS_REG_ADDR(SPI_FLASH_USR)
#define P_SPI_FLASH_USR_ADDR CBUS_REG_ADDR(SPI_FLASH_USR_ADDR)
#define P_SPI_FLASH_USR_DUMMY CBUS_REG_ADDR(SPI_FLASH_USR_DUMMY)
#define P_SPI_FLASH_USR_DIN CBUS_REG_ADDR(SPI_FLASH_USR_DIN)
#define P_SPI_FLASH_USR_DOUT CBUS_REG_ADDR(SPI_FLASH_USR_DOUT)
#define P_SPI_FLASH_USR_DUMMY_BLEN CBUS_REG_ADDR(SPI_FLASH_USR_DUMMY_BLEN)
#define P_SPI_FLASH_USR_CMD CBUS_REG_ADDR(SPI_FLASH_USR_CMD)
#define P_SPI_FLASH_ADDR CBUS_REG_ADDR(SPI_FLASH_ADDR)
#define P_SPI_FLASH_BYTES_LEN CBUS_REG_ADDR(SPI_FLASH_BYTES_LEN)
#define P_SPI_FLASH_ADDR_START CBUS_REG_ADDR(SPI_FLASH_ADDR_START)
#define P_SPI_FLASH_CTRL CBUS_REG_ADDR(SPI_FLASH_CTRL)
#define P_SPI_ENABLE_AHB CBUS_REG_ADDR(SPI_ENABLE_AHB)
#define P_SPI_SST_AAI CBUS_REG_ADDR(SPI_SST_AAI)
#define P_SPI_RES_RID CBUS_REG_ADDR(SPI_RES_RID)
#define P_SPI_FREAD_DUAL CBUS_REG_ADDR(SPI_FREAD_DUAL)
#define P_SPI_READ_READ_EN CBUS_REG_ADDR(SPI_READ_READ_EN)
#define P_SPI_CLK_DIV0 CBUS_REG_ADDR(SPI_CLK_DIV0)
#define P_SPI_CLKCNT_N CBUS_REG_ADDR(SPI_CLKCNT_N)
#define P_SPI_CLKCNT_H CBUS_REG_ADDR(SPI_CLKCNT_H)
#define P_SPI_CLKCNT_L CBUS_REG_ADDR(SPI_CLKCNT_L)
#define P_SPI_FLASH_CTRL1 CBUS_REG_ADDR(SPI_FLASH_CTRL1)
#define P_SPI_FLASH_STATUS CBUS_REG_ADDR(SPI_FLASH_STATUS)
#define P_SPI_FLASH_CTRL2 CBUS_REG_ADDR(SPI_FLASH_CTRL2)
#define P_SPI_FLASH_CLOCK CBUS_REG_ADDR(SPI_FLASH_CLOCK)
#define P_SPI_FLASH_USER CBUS_REG_ADDR(SPI_FLASH_USER)
#define P_SPI_FLASH_USER1 CBUS_REG_ADDR(SPI_FLASH_USER1)
#define P_SPI_FLASH_USER2 CBUS_REG_ADDR(SPI_FLASH_USER2)
#define P_SPI_FLASH_USER3 CBUS_REG_ADDR(SPI_FLASH_USER3)
#define P_SPI_FLASH_USER4 CBUS_REG_ADDR(SPI_FLASH_USER4)
#define P_SPI_FLASH_SLAVE CBUS_REG_ADDR(SPI_FLASH_SLAVE)
#define P_SPI_FLASH_SLAVE1 CBUS_REG_ADDR(SPI_FLASH_SLAVE1)
#define P_SPI_FLASH_SLAVE2 CBUS_REG_ADDR(SPI_FLASH_SLAVE2)
#define P_SPI_FLASH_SLAVE3 CBUS_REG_ADDR(SPI_FLASH_SLAVE3)
#define P_SPI_FLASH_C0 CBUS_REG_ADDR(SPI_FLASH_C0)
#define P_SPI_FLASH_C1 CBUS_REG_ADDR(SPI_FLASH_C1)
#define P_SPI_FLASH_C2 CBUS_REG_ADDR(SPI_FLASH_C2)
#define P_SPI_FLASH_C3 CBUS_REG_ADDR(SPI_FLASH_C3)
#define P_SPI_FLASH_C4 CBUS_REG_ADDR(SPI_FLASH_C4)
#define P_SPI_FLASH_C5 CBUS_REG_ADDR(SPI_FLASH_C5)
#define P_SPI_FLASH_C6 CBUS_REG_ADDR(SPI_FLASH_C6)
#define P_SPI_FLASH_C7 CBUS_REG_ADDR(SPI_FLASH_C7)
#define P_SPI_FLASH_B8 CBUS_REG_ADDR(SPI_FLASH_B8)
#define P_SPI_FLASH_B9 CBUS_REG_ADDR(SPI_FLASH_B9)
#define P_SPI_FLASH_B10 CBUS_REG_ADDR(SPI_FLASH_B10)
#define P_SPI_FLASH_B11 CBUS_REG_ADDR(SPI_FLASH_B11)
#define P_SPI_FLASH_B12 CBUS_REG_ADDR(SPI_FLASH_B12)
#define P_SPI_FLASH_B13 CBUS_REG_ADDR(SPI_FLASH_B13)
#define P_SPI_FLASH_B14 CBUS_REG_ADDR(SPI_FLASH_B14)
#define P_SPI_FLASH_B15 CBUS_REG_ADDR(SPI_FLASH_B15)
#define P_SPI2_FLASH_CMD CBUS_REG_ADDR(SPI2_FLASH_CMD)
#define P_SPI2_FLASH_ADDR CBUS_REG_ADDR(SPI2_FLASH_ADDR)
#define P_SPI2_FLASH_CTRL CBUS_REG_ADDR(SPI2_FLASH_CTRL)
#define P_SPI2_FLASH_CTRL1 CBUS_REG_ADDR(SPI2_FLASH_CTRL1)
#define P_SPI2_FLASH_STATUS CBUS_REG_ADDR(SPI2_FLASH_STATUS)
#define P_SPI2_FLASH_CTRL2 CBUS_REG_ADDR(SPI2_FLASH_CTRL2)
#define P_SPI2_FLASH_CLOCK CBUS_REG_ADDR(SPI2_FLASH_CLOCK)
#define P_SPI2_FLASH_USER CBUS_REG_ADDR(SPI2_FLASH_USER)
#define P_SPI2_FLASH_USER1 CBUS_REG_ADDR(SPI2_FLASH_USER1)
#define P_SPI2_FLASH_USER2 CBUS_REG_ADDR(SPI2_FLASH_USER2)
#define P_SPI2_FLASH_USER3 CBUS_REG_ADDR(SPI2_FLASH_USER3)
#define P_SPI2_FLASH_USER4 CBUS_REG_ADDR(SPI2_FLASH_USER4)
#define P_SPI2_FLASH_SLAVE CBUS_REG_ADDR(SPI2_FLASH_SLAVE)
#define P_SPI2_FLASH_SLAVE1 CBUS_REG_ADDR(SPI2_FLASH_SLAVE1)
#define P_SPI2_FLASH_SLAVE2 CBUS_REG_ADDR(SPI2_FLASH_SLAVE2)
#define P_SPI2_FLASH_SLAVE3 CBUS_REG_ADDR(SPI2_FLASH_SLAVE3)
#define P_SPI2_FLASH_C0 CBUS_REG_ADDR(SPI2_FLASH_C0)
#define P_SPI2_FLASH_C1 CBUS_REG_ADDR(SPI2_FLASH_C1)
#define P_SPI2_FLASH_C2 CBUS_REG_ADDR(SPI2_FLASH_C2)
#define P_SPI2_FLASH_C3 CBUS_REG_ADDR(SPI2_FLASH_C3)
#define P_SPI2_FLASH_C4 CBUS_REG_ADDR(SPI2_FLASH_C4)
#define P_SPI2_FLASH_C5 CBUS_REG_ADDR(SPI2_FLASH_C5)
#define P_SPI2_FLASH_C6 CBUS_REG_ADDR(SPI2_FLASH_C6)
#define P_SPI2_FLASH_C7 CBUS_REG_ADDR(SPI2_FLASH_C7)
#define P_SPI2_FLASH_B8 CBUS_REG_ADDR(SPI2_FLASH_B8)
#define P_SPI2_FLASH_B9 CBUS_REG_ADDR(SPI2_FLASH_B9)
#define P_SPI2_FLASH_B10 CBUS_REG_ADDR(SPI2_FLASH_B10)
#define P_SPI2_FLASH_B11 CBUS_REG_ADDR(SPI2_FLASH_B11)
#define P_SPI2_FLASH_B12 CBUS_REG_ADDR(SPI2_FLASH_B12)
#define P_SPI2_FLASH_B13 CBUS_REG_ADDR(SPI2_FLASH_B13)
#define P_SPI2_FLASH_B14 CBUS_REG_ADDR(SPI2_FLASH_B14)
#define P_SPI2_FLASH_B15 CBUS_REG_ADDR(SPI2_FLASH_B15)
#define P_ISA_DEBUG_REG0 CBUS_REG_ADDR(ISA_DEBUG_REG0)
#define P_ISA_DEBUG_REG1 CBUS_REG_ADDR(ISA_DEBUG_REG1)
#define P_ISA_DEBUG_REG2 CBUS_REG_ADDR(ISA_DEBUG_REG2)
#define P_ISA_PLL_CLK_SIM0 CBUS_REG_ADDR(ISA_PLL_CLK_SIM0)
#define P_ISA_CNTL_REG0 CBUS_REG_ADDR(ISA_CNTL_REG0)
#define P_AUD_ARC_IRQ_IN0_INTR_STAT CBUS_REG_ADDR(AUD_ARC_IRQ_IN0_INTR_STAT)
#define P_AUD_ARC_IRQ_IN0_INTR_STAT_CLR CBUS_REG_ADDR(AUD_ARC_IRQ_IN0_INTR_STAT_CLR)
#define P_AUD_ARC_IRQ_IN0_INTR_MASK CBUS_REG_ADDR(AUD_ARC_IRQ_IN0_INTR_MASK)
#define P_INT_USB1 CBUS_REG_ADDR(INT_USB1)
#define P_INT_USB0 CBUS_REG_ADDR(INT_USB0)
#define P_INT_TIMERD CBUS_REG_ADDR(INT_TIMERD)
#define P_INT_DVIN CBUS_REG_ADDR(INT_DVIN)
#define P_INT_UART CBUS_REG_ADDR(INT_UART)
#define P_INT_ASYNC_FIFO2_FLUSH CBUS_REG_ADDR(INT_ASYNC_FIFO2_FLUSH)
#define P_INT_ASYNC_FIFO2_FILL CBUS_REG_ADDR(INT_ASYNC_FIFO2_FILL)
#define P_INT_DEMUX CBUS_REG_ADDR(INT_DEMUX)
#define P_INT_ENCODER_IF CBUS_REG_ADDR(INT_ENCODER_IF)
#define P_INT_M_I2C_IRQ CBUS_REG_ADDR(INT_M_I2C_IRQ)
#define P_INT_BTR656 CBUS_REG_ADDR(INT_BTR656)
#define P_INT_ASYNC_FIFO_FLUSH CBUS_REG_ADDR(INT_ASYNC_FIFO_FLUSH)
#define P_INT_ASYNC_FIFO_FILL CBUS_REG_ADDR(INT_ASYNC_FIFO_FILL)
#define P_INT_ABUF_RD CBUS_REG_ADDR(INT_ABUF_RD)
#define P_INT_ABUF_WR CBUS_REG_ADDR(INT_ABUF_WR)
#define P_INT_IR_DEC_IRQ CBUS_REG_ADDR(INT_IR_DEC_IRQ)
#define P_INT_BLKMV CBUS_REG_ADDR(INT_BLKMV)
#define P_INT_NDMA_IRQ CBUS_REG_ADDR(INT_NDMA_IRQ)
#define P_INT_IDE CBUS_REG_ADDR(INT_IDE)
#define P_INT_TIMERB CBUS_REG_ADDR(INT_TIMERB)
#define P_INT_TIMERA CBUS_REG_ADDR(INT_TIMERA)
#define P_INT_RDS_IRQ CBUS_REG_ADDR(INT_RDS_IRQ)
#define P_INT_AUDIN CBUS_REG_ADDR(INT_AUDIN)
#define P_INT_TIMERC CBUS_REG_ADDR(INT_TIMERC)
#define P_INT_VFD_IRQ CBUS_REG_ADDR(INT_VFD_IRQ)
#define P_INT_IRQ14 CBUS_REG_ADDR(INT_IRQ14)
#define P_INT_VSYNC CBUS_REG_ADDR(INT_VSYNC)
#define P_INT_HSYNC CBUS_REG_ADDR(INT_HSYNC)
#define P_INT_MAILBOX CBUS_REG_ADDR(INT_MAILBOX)
#define P_AUD_ARC_IRQ_IN0_INTR_FIRQ_SEL CBUS_REG_ADDR(AUD_ARC_IRQ_IN0_INTR_FIRQ_SEL)
#define P_AUD_ARC_IRQ_IN1_INTR_STAT CBUS_REG_ADDR(AUD_ARC_IRQ_IN1_INTR_STAT)
#define P_AUD_ARC_IRQ_IN1_INTR_STAT_CLR CBUS_REG_ADDR(AUD_ARC_IRQ_IN1_INTR_STAT_CLR)
#define P_AUD_ARC_IRQ_IN1_INTR_MASK CBUS_REG_ADDR(AUD_ARC_IRQ_IN1_INTR_MASK)
#define P_AUD_ARC_IRQ_IN1_INTR_FIRQ_SEL CBUS_REG_ADDR(AUD_ARC_IRQ_IN1_INTR_FIRQ_SEL)
#define P_AUD_ARC_IRQ_IN2_INTR_STAT CBUS_REG_ADDR(AUD_ARC_IRQ_IN2_INTR_STAT)
#define P_AUD_ARC_IRQ_IN2_INTR_STAT_CLR CBUS_REG_ADDR(AUD_ARC_IRQ_IN2_INTR_STAT_CLR)
#define P_AUD_ARC_IRQ_IN2_INTR_MASK CBUS_REG_ADDR(AUD_ARC_IRQ_IN2_INTR_MASK)
#define P_AUD_ARC_IRQ_IN2_INTR_FIRQ_SEL CBUS_REG_ADDR(AUD_ARC_IRQ_IN2_INTR_FIRQ_SEL)
#define P_AUD_ARC_IRQ_IN3_INTR_STAT CBUS_REG_ADDR(AUD_ARC_IRQ_IN3_INTR_STAT)
#define P_AUD_ARC_IRQ_IN3_INTR_STAT_CLR CBUS_REG_ADDR(AUD_ARC_IRQ_IN3_INTR_STAT_CLR)
#define P_AUD_ARC_IRQ_IN3_INTR_MASK CBUS_REG_ADDR(AUD_ARC_IRQ_IN3_INTR_MASK)
#define P_AUD_ARC_IRQ_IN3_INTR_FIRQ_SEL CBUS_REG_ADDR(AUD_ARC_IRQ_IN3_INTR_FIRQ_SEL)
#define P_GPIO_INTR_EDGE_POL CBUS_REG_ADDR(GPIO_INTR_EDGE_POL)
#define P_GPIO_INTR_GPIO_SEL0 CBUS_REG_ADDR(GPIO_INTR_GPIO_SEL0)
#define P_GPIO_INTR_GPIO_SEL1 CBUS_REG_ADDR(GPIO_INTR_GPIO_SEL1)
#define P_GPIO_INTR_FILTER_SEL0 CBUS_REG_ADDR(GPIO_INTR_FILTER_SEL0)
#define P_GLOBAL_INTR_DISABLE CBUS_REG_ADDR(GLOBAL_INTR_DISABLE)
#define P_WATCHDOG_TC CBUS_REG_ADDR(WATCHDOG_TC)
#define P_WATCHDOG_RESET CBUS_REG_ADDR(WATCHDOG_RESET_REG)
#define P_AHB_ARBITER_REG CBUS_REG_ADDR(AHB_ARBITER_REG)
#define P_AHB_ARBDEC_REG CBUS_REG_ADDR(AHB_ARBDEC_REG)
#define P_ISA_BIST_REG0 CBUS_REG_ADDR(ISA_BIST_REG0)
#define P_ISA_BIST_REG1 CBUS_REG_ADDR(ISA_BIST_REG1)
#define P_ISA_BIST_REG2 CBUS_REG_ADDR(ISA_BIST_REG2)
#define P_ISA_BIST_REG3 CBUS_REG_ADDR(ISA_BIST_REG3)
#define P_ISA_BIST_REG4 CBUS_REG_ADDR(ISA_BIST_REG4)
#define P_ISA_BIST_REG5 CBUS_REG_ADDR(ISA_BIST_REG5)
#define P_ISA_TIMER_MUX CBUS_REG_ADDR(ISA_TIMER_MUX)
#define P_ISA_TIMERA CBUS_REG_ADDR(ISA_TIMERA)
#define P_ISA_TIMERB CBUS_REG_ADDR(ISA_TIMERB)
#define P_ISA_TIMERC CBUS_REG_ADDR(ISA_TIMERC)
#define P_ISA_TIMERD CBUS_REG_ADDR(ISA_TIMERD)
#define P_ISA_TIMERE CBUS_REG_ADDR(ISA_TIMERE)
#define P_FBUF_ADDR CBUS_REG_ADDR(FBUF_ADDR)
#define P_VIDEO_FRM_BUF_MSB_BIT CBUS_REG_ADDR(VIDEO_FRM_BUF_MSB_BIT)
#define P_VIDEO_FRM_BUF_LSB_BIT CBUS_REG_ADDR(VIDEO_FRM_BUF_LSB_BIT)
#define P_SDRAM_CTL0 CBUS_REG_ADDR(SDRAM_CTL0)
#define P_SDRAM_CTL2 CBUS_REG_ADDR(SDRAM_CTL2)
#define P_AUD_ARC_CTL CBUS_REG_ADDR(AUD_ARC_CTL)
#define P_SDRAM_CTL4 CBUS_REG_ADDR(SDRAM_CTL4)
#define P_SDRAM_CTL5 CBUS_REG_ADDR(SDRAM_CTL5)
#define P_SDRAM_CTL6 CBUS_REG_ADDR(SDRAM_CTL6)
#define P_SDRAM_CTL7 CBUS_REG_ADDR(SDRAM_CTL7)
#define P_SDRAM_CTL8 CBUS_REG_ADDR(SDRAM_CTL8)
#define P_AHB_MP4_MC_CTL CBUS_REG_ADDR(AHB_MP4_MC_CTL)
#define P_AUD_ARC_PCR CBUS_REG_ADDR(AUD_ARC_PCR)
#define P_ABUF_WR_CTL0 CBUS_REG_ADDR(ABUF_WR_CTL0)
#define P_ABUF_WR_INT_EN CBUS_REG_ADDR(ABUF_WR_INT_EN)
#define P_ABUF_WR_INT_POS_MSB CBUS_REG_ADDR(ABUF_WR_INT_POS_MSB)
#define P_ABUF_WR_INT_POS_LSB CBUS_REG_ADDR(ABUF_WR_INT_POS_LSB)
#define P_ABUF_WR_BLK_SIZE_MSB CBUS_REG_ADDR(ABUF_WR_BLK_SIZE_MSB)
#define P_ABUF_WR_BLK_SIZE_LSB CBUS_REG_ADDR(ABUF_WR_BLK_SIZE_LSB)
#define P_ABUF_WR_CTL1 CBUS_REG_ADDR(ABUF_WR_CTL1)
#define P_ABUF_WR_INT_EN CBUS_REG_ADDR(ABUF_WR_INT_EN)
#define P_ABUF_WR_INT_POS_MSB CBUS_REG_ADDR(ABUF_WR_INT_POS_MSB)
#define P_ABUF_WR_INT_POS_LSB CBUS_REG_ADDR(ABUF_WR_INT_POS_LSB)
#define P_ABUF_WR_BLK_SIZE_MSB CBUS_REG_ADDR(ABUF_WR_BLK_SIZE_MSB)
#define P_ABUF_WR_BLK_SIZE_LSB CBUS_REG_ADDR(ABUF_WR_BLK_SIZE_LSB)
#define P_ABUF_WR_CTL2 CBUS_REG_ADDR(ABUF_WR_CTL2)
#define P_ABUF_WR_CUR_FF_CNT_MSB CBUS_REG_ADDR(ABUF_WR_CUR_FF_CNT_MSB)
#define P_ABUF_WR_CUR_FF_CNT_LSB CBUS_REG_ADDR(ABUF_WR_CUR_FF_CNT_LSB)
#define P_ABUF_WR_CUR_BLK_MSB CBUS_REG_ADDR(ABUF_WR_CUR_BLK_MSB)
#define P_ABUF_WR_CUR_BLK_LSB CBUS_REG_ADDR(ABUF_WR_CUR_BLK_LSB)
#define P_ABUF_WR_CTL3 CBUS_REG_ADDR(ABUF_WR_CTL3)
#define P_ABUF_WR_AHB_RST_PLS CBUS_REG_ADDR(ABUF_WR_AHB_RST_PLS)
#define P_ABUF_WR_FF_CLR_PLS CBUS_REG_ADDR(ABUF_WR_FF_CLR_PLS)
#define P_ABUF_WR_PLY_RPT_LVL CBUS_REG_ADDR(ABUF_WR_PLY_RPT_LVL)
#define P_ABUF_WR_FF_PAUSE_LVL CBUS_REG_ADDR(ABUF_WR_FF_PAUSE_LVL)
#define P_ABUF_RD_CTL0 CBUS_REG_ADDR(ABUF_RD_CTL0)
#define P_ABUF_RD_CTL1 CBUS_REG_ADDR(ABUF_RD_CTL1)
#define P_ABUF_RD_INT_EN CBUS_REG_ADDR(ABUF_RD_INT_EN)
#define P_ABUF_RD_INT_POS_MSB CBUS_REG_ADDR(ABUF_RD_INT_POS_MSB)
#define P_ABUF_RD_INT_POS_LSB CBUS_REG_ADDR(ABUF_RD_INT_POS_LSB)
#define P_ABUF_RD_BLK_SIZE_MSB CBUS_REG_ADDR(ABUF_RD_BLK_SIZE_MSB)
#define P_ABUF_RD_BLK_SIZE_LSB CBUS_REG_ADDR(ABUF_RD_BLK_SIZE_LSB)
#define P_ABUF_RD_CTL2 CBUS_REG_ADDR(ABUF_RD_CTL2)
#define P_ABUF_RD_CUR_FF_CNT_MSB CBUS_REG_ADDR(ABUF_RD_CUR_FF_CNT_MSB)
#define P_ABUF_RD_CUR_FF_CNT_LSB CBUS_REG_ADDR(ABUF_RD_CUR_FF_CNT_LSB)
#define P_ABUF_RD_CUR_BLK_MSB CBUS_REG_ADDR(ABUF_RD_CUR_BLK_MSB)
#define P_ABUF_RD_CUR_BLK_LSB CBUS_REG_ADDR(ABUF_RD_CUR_BLK_LSB)
#define P_ABUF_RD_CTL3 CBUS_REG_ADDR(ABUF_RD_CTL3)
#define P_ABUF_RD_PLY_ONCE_PLS CBUS_REG_ADDR(ABUF_RD_PLY_ONCE_PLS)
#define P_ABUF_RD_AHB_RST_PLS CBUS_REG_ADDR(ABUF_RD_AHB_RST_PLS)
#define P_ABUF_RD_FF_CLR_PLS CBUS_REG_ADDR(ABUF_RD_FF_CLR_PLS)
#define P_ABUF_RD_PLY_RPT_LVL CBUS_REG_ADDR(ABUF_RD_PLY_RPT_LVL)
#define P_ABUF_RD_FF_PAUSE_LVL CBUS_REG_ADDR(ABUF_RD_FF_PAUSE_LVL)
#define P_ABUF_ARB_CTL0 CBUS_REG_ADDR(ABUF_ARB_CTL0)
#define P_ABUF_FIFO_CTL0 CBUS_REG_ADDR(ABUF_FIFO_CTL0)
#define P_AIUout_FIFO_THRESHOLD_MSB CBUS_REG_ADDR(AIUout_FIFO_THRESHOLD_MSB)
#define P_AIUout_FIFO_THRESHOLD_LSB CBUS_REG_ADDR(AIUout_FIFO_THRESHOLD_LSB)
#define P_AIUin_FIFO_THRESHOLD_MSB CBUS_REG_ADDR(AIUin_FIFO_THRESHOLD_MSB)
#define P_AIUin_FIFO_THRESHOLD_LSB CBUS_REG_ADDR(AIUin_FIFO_THRESHOLD_LSB)
#define P_AHB_BRIDGE_CNTL_WR CBUS_REG_ADDR(AHB_BRIDGE_CNTL_WR)
#define P_AHB_BRIDGE_REMAP0 CBUS_REG_ADDR(AHB_BRIDGE_REMAP0)
#define P_AHB_BRIDGE_REMAP1 CBUS_REG_ADDR(AHB_BRIDGE_REMAP1)
#define P_AHB_BRIDGE_REMAP2 CBUS_REG_ADDR(AHB_BRIDGE_REMAP2)
#define P_AHB_BRIDGE_REMAP3 CBUS_REG_ADDR(AHB_BRIDGE_REMAP3)
#define P_AHB_BRIDGE_CNTL_REG1 CBUS_REG_ADDR(AHB_BRIDGE_CNTL_REG1)
#define P_A9_0_IRQ_IN0_INTR_STAT CBUS_REG_ADDR(A9_0_IRQ_IN0_INTR_STAT)
#define P_A9_0_IRQ_IN0_INTR_STAT_CLR CBUS_REG_ADDR(A9_0_IRQ_IN0_INTR_STAT_CLR)
#define P_A9_0_IRQ_IN0_INTR_MASK CBUS_REG_ADDR(A9_0_IRQ_IN0_INTR_MASK)
#define P_A9_0_IRQ_IN0_INTR_FIRQ_SEL CBUS_REG_ADDR(A9_0_IRQ_IN0_INTR_FIRQ_SEL)
#define P_A9_0_IRQ_IN1_INTR_STAT CBUS_REG_ADDR(A9_0_IRQ_IN1_INTR_STAT)
#define P_A9_0_IRQ_IN1_INTR_STAT_CLR CBUS_REG_ADDR(A9_0_IRQ_IN1_INTR_STAT_CLR)
#define P_A9_0_IRQ_IN1_INTR_MASK CBUS_REG_ADDR(A9_0_IRQ_IN1_INTR_MASK)
#define P_A9_0_IRQ_IN1_INTR_FIRQ_SEL CBUS_REG_ADDR(A9_0_IRQ_IN1_INTR_FIRQ_SEL)
#define P_A9_0_IRQ_IN2_INTR_STAT CBUS_REG_ADDR(A9_0_IRQ_IN2_INTR_STAT)
#define P_A9_0_IRQ_IN2_INTR_STAT_CLR CBUS_REG_ADDR(A9_0_IRQ_IN2_INTR_STAT_CLR)
#define P_A9_0_IRQ_IN2_INTR_MASK CBUS_REG_ADDR(A9_0_IRQ_IN2_INTR_MASK)
#define P_A9_0_IRQ_IN2_INTR_FIRQ_SEL CBUS_REG_ADDR(A9_0_IRQ_IN2_INTR_FIRQ_SEL)
#define P_A9_0_IRQ_IN3_INTR_STAT CBUS_REG_ADDR(A9_0_IRQ_IN3_INTR_STAT)
#define P_A9_0_IRQ_IN3_INTR_STAT_CLR CBUS_REG_ADDR(A9_0_IRQ_IN3_INTR_STAT_CLR)
#define P_A9_0_IRQ_IN3_INTR_MASK CBUS_REG_ADDR(A9_0_IRQ_IN3_INTR_MASK)
#define P_A9_0_IRQ_IN3_INTR_FIRQ_SEL CBUS_REG_ADDR(A9_0_IRQ_IN3_INTR_FIRQ_SEL)
#define P_A9_1_IRQ_IN0_INTR_STAT CBUS_REG_ADDR(A9_1_IRQ_IN0_INTR_STAT)
#define P_A9_1_IRQ_IN0_INTR_STAT_CLR CBUS_REG_ADDR(A9_1_IRQ_IN0_INTR_STAT_CLR)
#define P_A9_1_IRQ_IN0_INTR_MASK CBUS_REG_ADDR(A9_1_IRQ_IN0_INTR_MASK)
#define P_A9_1_IRQ_IN0_INTR_FIRQ_SEL CBUS_REG_ADDR(A9_1_IRQ_IN0_INTR_FIRQ_SEL)
#define P_A9_1_IRQ_IN1_INTR_STAT CBUS_REG_ADDR(A9_1_IRQ_IN1_INTR_STAT)
#define P_A9_1_IRQ_IN1_INTR_STAT_CLR CBUS_REG_ADDR(A9_1_IRQ_IN1_INTR_STAT_CLR)
#define P_A9_1_IRQ_IN1_INTR_MASK CBUS_REG_ADDR(A9_1_IRQ_IN1_INTR_MASK)
#define P_A9_1_IRQ_IN1_INTR_FIRQ_SEL CBUS_REG_ADDR(A9_1_IRQ_IN1_INTR_FIRQ_SEL)
#define P_A9_1_IRQ_IN2_INTR_STAT CBUS_REG_ADDR(A9_1_IRQ_IN2_INTR_STAT)
#define P_A9_1_IRQ_IN2_INTR_STAT_CLR CBUS_REG_ADDR(A9_1_IRQ_IN2_INTR_STAT_CLR)
#define P_A9_1_IRQ_IN2_INTR_MASK CBUS_REG_ADDR(A9_1_IRQ_IN2_INTR_MASK)
#define P_A9_1_IRQ_IN2_INTR_FIRQ_SEL CBUS_REG_ADDR(A9_1_IRQ_IN2_INTR_FIRQ_SEL)
#define P_A9_1_IRQ_IN3_INTR_STAT CBUS_REG_ADDR(A9_1_IRQ_IN3_INTR_STAT)
#define P_A9_1_IRQ_IN3_INTR_STAT_CLR CBUS_REG_ADDR(A9_1_IRQ_IN3_INTR_STAT_CLR)
#define P_A9_1_IRQ_IN3_INTR_MASK CBUS_REG_ADDR(A9_1_IRQ_IN3_INTR_MASK)
#define P_A9_1_IRQ_IN3_INTR_FIRQ_SEL CBUS_REG_ADDR(A9_1_IRQ_IN3_INTR_FIRQ_SEL)
#define P_IQ_OM_WIDTH CBUS_REG_ADDR(IQ_OM_WIDTH)
#define P_DBG_ADDR_START CBUS_REG_ADDR(DBG_ADDR_START)
#define P_DBG_ADDR_END CBUS_REG_ADDR(DBG_ADDR_END)
#define P_DBG_CTRL CBUS_REG_ADDR(DBG_CTRL)
#define P_DBG_LED CBUS_REG_ADDR(DBG_LED)
#define P_DBG_SWITCH CBUS_REG_ADDR(DBG_SWITCH)
#define P_DBG_VERSION CBUS_REG_ADDR(DBG_VERSION)
#define P_VERSION_CTRL CBUS_REG_ADDR(VERSION_CTRL)
#define P_RESET0_REGISTER CBUS_REG_ADDR(RESET0_REGISTER)
#define P_RESET1_REGISTER CBUS_REG_ADDR(RESET1_REGISTER)
#define P_RESET2_REGISTER CBUS_REG_ADDR(RESET2_REGISTER)
#define P_RESET3_REGISTER CBUS_REG_ADDR(RESET3_REGISTER)
#define P_RESET4_REGISTER CBUS_REG_ADDR(RESET4_REGISTER)
#define P_HIU_RESET CBUS_REG_ADDR(HIU_RESET)
#define P_VLD_RESET CBUS_REG_ADDR(VLD_RESET)
#define P_IQIDCT_RESET CBUS_REG_ADDR(IQIDCT_RESET)
#define P_MC_RESET CBUS_REG_ADDR(MC_RESET)
#define P_DCU_RESET CBUS_REG_ADDR(DCU_RESET)
#define P_VIU_RESET CBUS_REG_ADDR(VIU_RESET)
#define P_AIU_RESET CBUS_REG_ADDR(AIU_RESET)
#define P_CPU_RESET CBUS_REG_ADDR(CPU_RESET)
#define P_AC3_RESET CBUS_REG_ADDR(AC3_RESET)
#define P_MPEG_RESET CBUS_REG_ADDR(MPEG_RESET)
#define P_SCR_HIU CBUS_REG_ADDR(SCR_HIU)
#define P_HPG_TIMER CBUS_REG_ADDR(HPG_TIMER)
#define P_HARM_ASB_MB0 CBUS_REG_ADDR(HARM_ASB_MB0)
#define P_HARM_ASB_MB1 CBUS_REG_ADDR(HARM_ASB_MB1)
#define P_HARM_ASB_MB2 CBUS_REG_ADDR(HARM_ASB_MB2)
#define P_HARM_ASB_MB3 CBUS_REG_ADDR(HARM_ASB_MB3)
#define P_HASB_ARM_MB0 CBUS_REG_ADDR(HASB_ARM_MB0)
#define P_HASB_ARM_MB1 CBUS_REG_ADDR(HASB_ARM_MB1)
#define P_HASB_ARM_MB2 CBUS_REG_ADDR(HASB_ARM_MB2)
#define P_HASB_ARM_MB3 CBUS_REG_ADDR(HASB_ARM_MB3)
#define P_HHI_TIMER90K CBUS_REG_ADDR(HHI_TIMER90K)
#define P_HHI_AUD_DAC_CTRL CBUS_REG_ADDR(HHI_AUD_DAC_CTRL)
#define P_HHI_VIID_PLL_CNTL4 CBUS_REG_ADDR(HHI_VIID_PLL_CNTL4)
#define P_HHI_VIID_PLL_CNTL CBUS_REG_ADDR(HHI_VIID_PLL_CNTL)
#define P_HHI_VIID_PLL_CNTL2 CBUS_REG_ADDR(HHI_VIID_PLL_CNTL2)
#define P_HHI_VIID_PLL_CNTL3 CBUS_REG_ADDR(HHI_VIID_PLL_CNTL3)
#define P_HHI_VIID_CLK_DIV CBUS_REG_ADDR(HHI_VIID_CLK_DIV)
#define P_HHI_VIID_CLK_CNTL CBUS_REG_ADDR(HHI_VIID_CLK_CNTL)
#define P_HHI_VIID_DIVIDER_CNTL CBUS_REG_ADDR(HHI_VIID_DIVIDER_CNTL)
#define P_HHI_SYS_PLL_CNTL2 CBUS_REG_ADDR(HHI_SYS_PLL_CNTL2)
#define P_HHI_AUD_PLL_CNTL2 CBUS_REG_ADDR(HHI_AUD_PLL_CNTL2)
#define P_HHI_VID_PLL_CNTL2 CBUS_REG_ADDR(HHI_VID_PLL_CNTL2)
#define P_HHI_GCLK_MPEG0 CBUS_REG_ADDR(HHI_GCLK_MPEG0)
#define P_HHI_GCLK_MPEG1 CBUS_REG_ADDR(HHI_GCLK_MPEG1)
#define P_HHI_GCLK_MPEG2 CBUS_REG_ADDR(HHI_GCLK_MPEG2)
#define P_HHI_GCLK_OTHER CBUS_REG_ADDR(HHI_GCLK_OTHER)
#define P_HHI_SYS_PLL_CNTL3 CBUS_REG_ADDR(HHI_SYS_PLL_CNTL3)
#define P_HHI_AUD_PLL_CNTL3 CBUS_REG_ADDR(HHI_AUD_PLL_CNTL3)
#define P_HHI_VID_PLL_CNTL3 CBUS_REG_ADDR(HHI_VID_PLL_CNTL3)
#define P_HHI_VID_CLK_DIV CBUS_REG_ADDR(HHI_VID_CLK_DIV)
#define P_HHI_SYS_PLL_CNTL CBUS_REG_ADDR(HHI_SYS_PLL_CNTL)
#define P_HHI_AUD_PLL_CNTL CBUS_REG_ADDR(HHI_AUD_PLL_CNTL)
#define P_HHI_VID_PLL_CNTL CBUS_REG_ADDR(HHI_VID_PLL_CNTL)
#define P_HHI_MPEG_CLK_CNTL CBUS_REG_ADDR(HHI_MPEG_CLK_CNTL)
#define P_HHI_AUD_CLK_CNTL CBUS_REG_ADDR(HHI_AUD_CLK_CNTL)
#define P_HHI_VID_CLK_CNTL CBUS_REG_ADDR(HHI_VID_CLK_CNTL)
#define P_HHI_WIFI_CLK_CNTL CBUS_REG_ADDR(HHI_WIFI_CLK_CNTL)
#define P_HHI_WIFI_PLL_CNTL CBUS_REG_ADDR(HHI_WIFI_PLL_CNTL)
#define P_HHI_WIFI_PLL_CNTL2 CBUS_REG_ADDR(HHI_WIFI_PLL_CNTL2)
#define P_HHI_WIFI_PLL_CNTL3 CBUS_REG_ADDR(HHI_WIFI_PLL_CNTL3)
#define P_HHI_VID_DIVIDER_CNTL CBUS_REG_ADDR(HHI_VID_DIVIDER_CNTL)
#define P_HHI_A9_CLK_CNTL CBUS_REG_ADDR(HHI_A9_CLK_CNTL)
#define P_HHI_DDR_PLL_CNTL CBUS_REG_ADDR(HHI_DDR_PLL_CNTL)
#define P_HHI_DDR_PLL_CNTL2 CBUS_REG_ADDR(HHI_DDR_PLL_CNTL2)
#define P_HHI_DDR_PLL_CNTL3 CBUS_REG_ADDR(HHI_DDR_PLL_CNTL3)
#define P_HHI_MALI_CLK_CNTL CBUS_REG_ADDR(HHI_MALI_CLK_CNTL)
#define P_HHI_DEMOD_PLL_CNTL CBUS_REG_ADDR(HHI_DEMOD_PLL_CNTL)
#define P_HHI_DEMOD_PLL_CNTL2 CBUS_REG_ADDR(HHI_DEMOD_PLL_CNTL2)
#define P_HHI_DEMOD_PLL_CNTL3 CBUS_REG_ADDR(HHI_DEMOD_PLL_CNTL3)
#define P_HHI_OTHER_PLL_CNTL CBUS_REG_ADDR(HHI_OTHER_PLL_CNTL)
#define P_HHI_OTHER_PLL_CNTL2 CBUS_REG_ADDR(HHI_OTHER_PLL_CNTL2)
#define P_HHI_OTHER_PLL_CNTL3 CBUS_REG_ADDR(HHI_OTHER_PLL_CNTL3)
#define P_HHI_HDMI_CLK_CNTL CBUS_REG_ADDR(HHI_HDMI_CLK_CNTL)
#define P_HHI_DEMOD_CLK_CNTL CBUS_REG_ADDR(HHI_DEMOD_CLK_CNTL)
#define P_HHI_SATA_CLK_CNTL CBUS_REG_ADDR(HHI_SATA_CLK_CNTL)
#define P_HHI_ETH_CLK_CNTL CBUS_REG_ADDR(HHI_ETH_CLK_CNTL)
#define P_HHI_A9_AUTO_CLK0 CBUS_REG_ADDR(HHI_A9_AUTO_CLK0)
#define P_HHI_A9_AUTO_CLK1 CBUS_REG_ADDR(HHI_A9_AUTO_CLK1)
#define P_HHI_ARC625_AUTO_CLK0 CBUS_REG_ADDR(HHI_ARC625_AUTO_CLK0)
#define P_HHI_ARC625_AUTO_CLK1 CBUS_REG_ADDR(HHI_ARC625_AUTO_CLK1)
#define P_HHI_HDMI_PLL_CNTL CBUS_REG_ADDR(HHI_HDMI_PLL_CNTL)
#define P_HHI_HDMI_PLL_CNTL1 CBUS_REG_ADDR(HHI_HDMI_PLL_CNTL1)
#define P_HHI_HDMI_PLL_CNTL2 CBUS_REG_ADDR(HHI_HDMI_PLL_CNTL2)
#define P_HHI_HDMI_AFC_CNTL CBUS_REG_ADDR(HHI_HDMI_AFC_CNTL)
#define P_HHI_AUD_PLL_MOD_CNTL0 CBUS_REG_ADDR(HHI_AUD_PLL_MOD_CNTL0)
#define P_HHI_AUD_PLL_MOD_LOW_TCNT CBUS_REG_ADDR(HHI_AUD_PLL_MOD_LOW_TCNT)
#define P_HHI_AUD_PLL_MOD_HIGH_TCNT CBUS_REG_ADDR(HHI_AUD_PLL_MOD_HIGH_TCNT)
#define P_HHI_AUD_PLL_MOD_NOM_TCNT CBUS_REG_ADDR(HHI_AUD_PLL_MOD_NOM_TCNT)
#define P_HHI_VID_PLL_MOD_CNTL0 CBUS_REG_ADDR(HHI_VID_PLL_MOD_CNTL0)
#define P_HHI_VID_PLL_MOD_LOW_TCNT CBUS_REG_ADDR(HHI_VID_PLL_MOD_LOW_TCNT)
#define P_HHI_VID_PLL_MOD_HIGH_TCNT CBUS_REG_ADDR(HHI_VID_PLL_MOD_HIGH_TCNT)
#define P_HHI_VID_PLL_MOD_NOM_TCNT CBUS_REG_ADDR(HHI_VID_PLL_MOD_NOM_TCNT)
#define P_HHI_JTAG_CONFIG CBUS_REG_ADDR(HHI_JTAG_CONFIG)
#define P_PARSER_CONTROL CBUS_REG_ADDR(PARSER_CONTROL)
#define P_PARSER_FETCH_ADDR CBUS_REG_ADDR(PARSER_FETCH_ADDR)
#define P_PARSER_FETCH_CMD CBUS_REG_ADDR(PARSER_FETCH_CMD)
#define P_PARSER_FETCH_STOP_ADDR CBUS_REG_ADDR(PARSER_FETCH_STOP_ADDR)
#define P_PARSER_FETCH_LEVEL CBUS_REG_ADDR(PARSER_FETCH_LEVEL)
#define P_PARSER_CONFIG CBUS_REG_ADDR(PARSER_CONFIG)
#define P_PFIFO_WR_PTR CBUS_REG_ADDR(PFIFO_WR_PTR)
#define P_PFIFO_RD_PTR CBUS_REG_ADDR(PFIFO_RD_PTR)
#define P_PFIFO_DATA CBUS_REG_ADDR(PFIFO_DATA)
#define P_PARSER_SEARCH_PATTERN CBUS_REG_ADDR(PARSER_SEARCH_PATTERN)
#define P_PARSER_SEARCH_MASK CBUS_REG_ADDR(PARSER_SEARCH_MASK)
#define P_PARSER_INT_ENABLE CBUS_REG_ADDR(PARSER_INT_ENABLE)
#define P_PARSER_INT_STATUS CBUS_REG_ADDR(PARSER_INT_STATUS)
#define P_PARSER_SCR_CTL CBUS_REG_ADDR(PARSER_SCR_CTL)
#define P_PARSER_SCR CBUS_REG_ADDR(PARSER_SCR)
#define P_PARSER_PARAMETER CBUS_REG_ADDR(PARSER_PARAMETER)
#define P_PARSER_INSERT_DATA CBUS_REG_ADDR(PARSER_INSERT_DATA)
#define P_VAS_STREAM_ID CBUS_REG_ADDR(VAS_STREAM_ID)
#define P_VIDEO_DTS CBUS_REG_ADDR(VIDEO_DTS)
#define P_VIDEO_PTS CBUS_REG_ADDR(VIDEO_PTS)
#define P_VIDEO_PTS_DTS_WR_PTR CBUS_REG_ADDR(VIDEO_PTS_DTS_WR_PTR)
#define P_AUDIO_PTS CBUS_REG_ADDR(AUDIO_PTS)
#define P_AUDIO_PTS_WR_PTR CBUS_REG_ADDR(AUDIO_PTS_WR_PTR)
#define P_PARSER_ES_CONTROL CBUS_REG_ADDR(PARSER_ES_CONTROL)
#define P_PFIFO_MONITOR CBUS_REG_ADDR(PFIFO_MONITOR)
#define P_PARSER_VIDEO_START_PTR CBUS_REG_ADDR(PARSER_VIDEO_START_PTR)
#define P_PARSER_VIDEO_END_PTR CBUS_REG_ADDR(PARSER_VIDEO_END_PTR)
#define P_PARSER_VIDEO_WP CBUS_REG_ADDR(PARSER_VIDEO_WP)
#define P_PARSER_VIDEO_RP CBUS_REG_ADDR(PARSER_VIDEO_RP)
#define P_PARSER_VIDEO_HOLE CBUS_REG_ADDR(PARSER_VIDEO_HOLE)
#define P_PARSER_AUDIO_START_PTR CBUS_REG_ADDR(PARSER_AUDIO_START_PTR)
#define P_PARSER_AUDIO_END_PTR CBUS_REG_ADDR(PARSER_AUDIO_END_PTR)
#define P_PARSER_AUDIO_WP CBUS_REG_ADDR(PARSER_AUDIO_WP)
#define P_PARSER_AUDIO_RP CBUS_REG_ADDR(PARSER_AUDIO_RP)
#define P_PARSER_AUDIO_HOLE CBUS_REG_ADDR(PARSER_AUDIO_HOLE)
#define P_PARSER_SUB_START_PTR CBUS_REG_ADDR(PARSER_SUB_START_PTR)
#define P_PARSER_SUB_END_PTR CBUS_REG_ADDR(PARSER_SUB_END_PTR)
#define P_PARSER_SUB_WP CBUS_REG_ADDR(PARSER_SUB_WP)
#define P_PARSER_SUB_RP CBUS_REG_ADDR(PARSER_SUB_RP)
#define P_PARSER_SUB_HOLE CBUS_REG_ADDR(PARSER_SUB_HOLE)
#define P_PARSER_FETCH_INFO CBUS_REG_ADDR(PARSER_FETCH_INFO)
#define P_PARSER_STATUS CBUS_REG_ADDR(PARSER_STATUS)
#define P_PARSER_AV_WRAP_COUNT CBUS_REG_ADDR(PARSER_AV_WRAP_COUNT)
#define P_WRRSP_PARSER CBUS_REG_ADDR(WRRSP_PARSER)
#define P_VDIN_SCALE_COEF_IDX CBUS_REG_ADDR(VDIN_SCALE_COEF_IDX)
#define P_VDIN_SCALE_COEF CBUS_REG_ADDR(VDIN_SCALE_COEF)
#define P_VDIN_COM_CTRL0 CBUS_REG_ADDR(VDIN_COM_CTRL0)
#define P_VDIN_ACTIVE_MAX_PIX_CNT_STATUS CBUS_REG_ADDR(VDIN_ACTIVE_MAX_PIX_CNT_STATUS)
#define P_VDIN_LCNT_STATUS CBUS_REG_ADDR(VDIN_LCNT_STATUS)
#define P_VDIN_COM_STATUS0 CBUS_REG_ADDR(VDIN_COM_STATUS0)
#define P_VDIN_COM_STATUS1 CBUS_REG_ADDR(VDIN_COM_STATUS1)
#define P_VDIN_LCNT_SHADOW_STATUS CBUS_REG_ADDR(VDIN_LCNT_SHADOW_STATUS)
#define P_VDIN_ASFIFO_CTRL0 CBUS_REG_ADDR(VDIN_ASFIFO_CTRL0)
#define P_VDIN_ASFIFO_CTRL1 CBUS_REG_ADDR(VDIN_ASFIFO_CTRL1)
#define P_VDIN_WIDTHM1I_WIDTHM1O CBUS_REG_ADDR(VDIN_WIDTHM1I_WIDTHM1O)
#define P_VDIN_SC_MISC_CTRL CBUS_REG_ADDR(VDIN_SC_MISC_CTRL)
#define P_VDIN_HSC_PHASE_STEP CBUS_REG_ADDR(VDIN_HSC_PHASE_STEP)
#define P_VDIN_HSC_INI_CTRL CBUS_REG_ADDR(VDIN_HSC_INI_CTRL)
#define P_VDIN_MATRIX_CTRL CBUS_REG_ADDR(VDIN_MATRIX_CTRL)
#define P_VDIN_MATRIX_COEF00_01 CBUS_REG_ADDR(VDIN_MATRIX_COEF00_01)
#define P_VDIN_MATRIX_COEF02_10 CBUS_REG_ADDR(VDIN_MATRIX_COEF02_10)
#define P_VDIN_MATRIX_COEF11_12 CBUS_REG_ADDR(VDIN_MATRIX_COEF11_12)
#define P_VDIN_MATRIX_COEF20_21 CBUS_REG_ADDR(VDIN_MATRIX_COEF20_21)
#define P_VDIN_MATRIX_COEF22 CBUS_REG_ADDR(VDIN_MATRIX_COEF22)
#define P_VDIN_MATRIX_OFFSET0_1 CBUS_REG_ADDR(VDIN_MATRIX_OFFSET0_1)
#define P_VDIN_MATRIX_OFFSET2 CBUS_REG_ADDR(VDIN_MATRIX_OFFSET2)
#define P_VDIN_MATRIX_PRE_OFFSET0_1 CBUS_REG_ADDR(VDIN_MATRIX_PRE_OFFSET0_1)
#define P_VDIN_MATRIX_PRE_OFFSET2 CBUS_REG_ADDR(VDIN_MATRIX_PRE_OFFSET2)
#define P_VDIN_LFIFO_CTRL CBUS_REG_ADDR(VDIN_LFIFO_CTRL)
#define P_VDIN_COM_GCLK_CTRL CBUS_REG_ADDR(VDIN_COM_GCLK_CTRL)
#define P_VDIN_WR_CTRL CBUS_REG_ADDR(VDIN_WR_CTRL)
#define P_VDIN_WR_H_START_END CBUS_REG_ADDR(VDIN_WR_H_START_END)
#define P_VDIN_WR_V_START_END CBUS_REG_ADDR(VDIN_WR_V_START_END)
#define P_VDIN_HIST_CTRL CBUS_REG_ADDR(VDIN_HIST_CTRL)
#define P_VDIN_HIST_H_START_END CBUS_REG_ADDR(VDIN_HIST_H_START_END)
#define P_VDIN_HIST_V_START_END CBUS_REG_ADDR(VDIN_HIST_V_START_END)
#define P_VDIN_HIST_MAX_MIN CBUS_REG_ADDR(VDIN_HIST_MAX_MIN)
#define P_VDIN_HIST_SPL_VAL CBUS_REG_ADDR(VDIN_HIST_SPL_VAL)
#define P_VDIN_HIST_SPL_PIX_CNT CBUS_REG_ADDR(VDIN_HIST_SPL_PIX_CNT)
#define P_VDIN_HIST_CHROMA_SUM CBUS_REG_ADDR(VDIN_HIST_CHROMA_SUM)
#define P_VDIN_DNLP_HIST00 CBUS_REG_ADDR(VDIN_DNLP_HIST00)
#define P_VDIN_DNLP_HIST01 CBUS_REG_ADDR(VDIN_DNLP_HIST01)
#define P_VDIN_DNLP_HIST02 CBUS_REG_ADDR(VDIN_DNLP_HIST02)
#define P_VDIN_DNLP_HIST03 CBUS_REG_ADDR(VDIN_DNLP_HIST03)
#define P_VDIN_DNLP_HIST04 CBUS_REG_ADDR(VDIN_DNLP_HIST04)
#define P_VDIN_DNLP_HIST05 CBUS_REG_ADDR(VDIN_DNLP_HIST05)
#define P_VDIN_DNLP_HIST06 CBUS_REG_ADDR(VDIN_DNLP_HIST06)
#define P_VDIN_DNLP_HIST07 CBUS_REG_ADDR(VDIN_DNLP_HIST07)
#define P_VDIN_DNLP_HIST08 CBUS_REG_ADDR(VDIN_DNLP_HIST08)
#define P_VDIN_DNLP_HIST09 CBUS_REG_ADDR(VDIN_DNLP_HIST09)
#define P_VDIN_DNLP_HIST10 CBUS_REG_ADDR(VDIN_DNLP_HIST10)
#define P_VDIN_DNLP_HIST11 CBUS_REG_ADDR(VDIN_DNLP_HIST11)
#define P_VDIN_DNLP_HIST12 CBUS_REG_ADDR(VDIN_DNLP_HIST12)
#define P_VDIN_DNLP_HIST13 CBUS_REG_ADDR(VDIN_DNLP_HIST13)
#define P_VDIN_DNLP_HIST14 CBUS_REG_ADDR(VDIN_DNLP_HIST14)
#define P_VDIN_DNLP_HIST15 CBUS_REG_ADDR(VDIN_DNLP_HIST15)
#define P_VDIN_DNLP_HIST16 CBUS_REG_ADDR(VDIN_DNLP_HIST16)
#define P_VDIN_DNLP_HIST17 CBUS_REG_ADDR(VDIN_DNLP_HIST17)
#define P_VDIN_DNLP_HIST18 CBUS_REG_ADDR(VDIN_DNLP_HIST18)
#define P_VDIN_DNLP_HIST19 CBUS_REG_ADDR(VDIN_DNLP_HIST19)
#define P_VDIN_DNLP_HIST20 CBUS_REG_ADDR(VDIN_DNLP_HIST20)
#define P_VDIN_DNLP_HIST21 CBUS_REG_ADDR(VDIN_DNLP_HIST21)
#define P_VDIN_DNLP_HIST22 CBUS_REG_ADDR(VDIN_DNLP_HIST22)
#define P_VDIN_DNLP_HIST23 CBUS_REG_ADDR(VDIN_DNLP_HIST23)
#define P_VDIN_DNLP_HIST24 CBUS_REG_ADDR(VDIN_DNLP_HIST24)
#define P_VDIN_DNLP_HIST25 CBUS_REG_ADDR(VDIN_DNLP_HIST25)
#define P_VDIN_DNLP_HIST26 CBUS_REG_ADDR(VDIN_DNLP_HIST26)
#define P_VDIN_DNLP_HIST27 CBUS_REG_ADDR(VDIN_DNLP_HIST27)
#define P_VDIN_DNLP_HIST28 CBUS_REG_ADDR(VDIN_DNLP_HIST28)
#define P_VDIN_DNLP_HIST29 CBUS_REG_ADDR(VDIN_DNLP_HIST29)
#define P_VDIN_DNLP_HIST30 CBUS_REG_ADDR(VDIN_DNLP_HIST30)
#define P_VDIN_DNLP_HIST31 CBUS_REG_ADDR(VDIN_DNLP_HIST31)
#define P_VDIN_BLKBAR_CTRL0 CBUS_REG_ADDR(VDIN_BLKBAR_CTRL0)
#define P_VDIN_BLKBAR_H_START_END CBUS_REG_ADDR(VDIN_BLKBAR_H_START_END)
#define P_VDIN_BLKBAR_V_START_END CBUS_REG_ADDR(VDIN_BLKBAR_V_START_END)
#define P_VDIN_BLKBAR_CNT_THRESHOLD CBUS_REG_ADDR(VDIN_BLKBAR_CNT_THRESHOLD)
#define P_VDIN_BLKBAR_ROW_TH1_TH2 CBUS_REG_ADDR(VDIN_BLKBAR_ROW_TH1_TH2)
#define P_VDIN_BLKBAR_IND_LEFT_START_END CBUS_REG_ADDR(VDIN_BLKBAR_IND_LEFT_START_END)
#define P_VDIN_BLKBAR_IND_RIGHT_START_END CBUS_REG_ADDR(VDIN_BLKBAR_IND_RIGHT_START_END)
#define P_VDIN_BLKBAR_IND_LEFT1_CNT CBUS_REG_ADDR(VDIN_BLKBAR_IND_LEFT1_CNT)
#define P_VDIN_BLKBAR_IND_LEFT2_CNT CBUS_REG_ADDR(VDIN_BLKBAR_IND_LEFT2_CNT)
#define P_VDIN_BLKBAR_IND_RIGHT1_CNT CBUS_REG_ADDR(VDIN_BLKBAR_IND_RIGHT1_CNT)
#define P_VDIN_BLKBAR_IND_RIGHT2_CNT CBUS_REG_ADDR(VDIN_BLKBAR_IND_RIGHT2_CNT)
#define P_VDIN_BLKBAR_STATUS0 CBUS_REG_ADDR(VDIN_BLKBAR_STATUS0)
#define P_VDIN_BLKBAR_STATUS1 CBUS_REG_ADDR(VDIN_BLKBAR_STATUS1)
#define P_DVIN_FRONT_END_CTRL CBUS_REG_ADDR(DVIN_FRONT_END_CTRL)
#define P_DVIN_HS_LEAD_VS_ODD CBUS_REG_ADDR(DVIN_HS_LEAD_VS_ODD)
#define P_DVIN_ACTIVE_START_PIX CBUS_REG_ADDR(DVIN_ACTIVE_START_PIX)
#define P_DVIN_ACTIVE_START_LINE CBUS_REG_ADDR(DVIN_ACTIVE_START_LINE)
#define P_DVIN_DISPLAY_SIZE CBUS_REG_ADDR(DVIN_DISPLAY_SIZE)
#define P_DVIN_CTRL_STAT CBUS_REG_ADDR(DVIN_CTRL_STAT)
#define P_DVIN_VCANV_TBL_ADDR CBUS_REG_ADDR(DVIN_VCANV_TBL_ADDR)
#define P_DVIN_VCANV_XY_START_ADDR CBUS_REG_ADDR(DVIN_VCANV_XY_START_ADDR)
#define P_MSP CBUS_REG_ADDR(MSP)
#define P_MPSR CBUS_REG_ADDR(MPSR)
#define P_MINT_VEC_BASE CBUS_REG_ADDR(MINT_VEC_BASE)
#define P_MCPU_INTR_GRP CBUS_REG_ADDR(MCPU_INTR_GRP)
#define P_MCPU_INTR_MSK CBUS_REG_ADDR(MCPU_INTR_MSK)
#define P_MCPU_INTR_REQ CBUS_REG_ADDR(MCPU_INTR_REQ)
#define P_MPC_P CBUS_REG_ADDR(MPC_P)
#define P_MPC_D CBUS_REG_ADDR(MPC_D)
#define P_MPC_E CBUS_REG_ADDR(MPC_E)
#define P_MPC_W CBUS_REG_ADDR(MPC_W)
#define P_MINDEX0_REG CBUS_REG_ADDR(MINDEX0_REG)
#define P_MINDEX1_REG CBUS_REG_ADDR(MINDEX1_REG)
#define P_MINDEX2_REG CBUS_REG_ADDR(MINDEX2_REG)
#define P_MINDEX3_REG CBUS_REG_ADDR(MINDEX3_REG)
#define P_MINDEX4_REG CBUS_REG_ADDR(MINDEX4_REG)
#define P_MINDEX5_REG CBUS_REG_ADDR(MINDEX5_REG)
#define P_MINDEX6_REG CBUS_REG_ADDR(MINDEX6_REG)
#define P_MINDEX7_REG CBUS_REG_ADDR(MINDEX7_REG)
#define P_MMIN_REG CBUS_REG_ADDR(MMIN_REG)
#define P_MMAX_REG CBUS_REG_ADDR(MMAX_REG)
#define P_MBREAK0_REG CBUS_REG_ADDR(MBREAK0_REG)
#define P_MBREAK1_REG CBUS_REG_ADDR(MBREAK1_REG)
#define P_MBREAK2_REG CBUS_REG_ADDR(MBREAK2_REG)
#define P_MBREAK3_REG CBUS_REG_ADDR(MBREAK3_REG)
#define P_MBREAK_TYPE CBUS_REG_ADDR(MBREAK_TYPE)
#define P_MBREAK_CTRL CBUS_REG_ADDR(MBREAK_CTRL)
#define P_MBREAK_STAUTS CBUS_REG_ADDR(MBREAK_STAUTS)
#define P_MDB_ADDR_REG CBUS_REG_ADDR(MDB_ADDR_REG)
#define P_MDB_DATA_REG CBUS_REG_ADDR(MDB_DATA_REG)
#define P_MDB_CTRL CBUS_REG_ADDR(MDB_CTRL)
#define P_MSFTINT0 CBUS_REG_ADDR(MSFTINT0)
#define P_MSFTINT1 CBUS_REG_ADDR(MSFTINT1)
#define P_CSP CBUS_REG_ADDR(CSP)
#define P_CPSR CBUS_REG_ADDR(CPSR)
#define P_CINT_VEC_BASE CBUS_REG_ADDR(CINT_VEC_BASE)
#define P_CCPU_INTR_GRP CBUS_REG_ADDR(CCPU_INTR_GRP)
#define P_CCPU_INTR_MSK CBUS_REG_ADDR(CCPU_INTR_MSK)
#define P_CCPU_INTR_REQ CBUS_REG_ADDR(CCPU_INTR_REQ)
#define P_CPC_P CBUS_REG_ADDR(CPC_P)
#define P_CPC_D CBUS_REG_ADDR(CPC_D)
#define P_CPC_E CBUS_REG_ADDR(CPC_E)
#define P_CPC_W CBUS_REG_ADDR(CPC_W)
#define P_CINDEX0_REG CBUS_REG_ADDR(CINDEX0_REG)
#define P_CINDEX1_REG CBUS_REG_ADDR(CINDEX1_REG)
#define P_CINDEX2_REG CBUS_REG_ADDR(CINDEX2_REG)
#define P_CINDEX3_REG CBUS_REG_ADDR(CINDEX3_REG)
#define P_CINDEX4_REG CBUS_REG_ADDR(CINDEX4_REG)
#define P_CINDEX5_REG CBUS_REG_ADDR(CINDEX5_REG)
#define P_CINDEX6_REG CBUS_REG_ADDR(CINDEX6_REG)
#define P_CINDEX7_REG CBUS_REG_ADDR(CINDEX7_REG)
#define P_CMIN_REG CBUS_REG_ADDR(CMIN_REG)
#define P_CMAX_REG CBUS_REG_ADDR(CMAX_REG)
#define P_CBREAK0_REG CBUS_REG_ADDR(CBREAK0_REG)
#define P_CBREAK1_REG CBUS_REG_ADDR(CBREAK1_REG)
#define P_CBREAK2_REG CBUS_REG_ADDR(CBREAK2_REG)
#define P_CBREAK3_REG CBUS_REG_ADDR(CBREAK3_REG)
#define P_CBREAK_TYPE CBUS_REG_ADDR(CBREAK_TYPE)
#define P_CBREAK_CTRL CBUS_REG_ADDR(CBREAK_CTRL)
#define P_CBREAK_STAUTS CBUS_REG_ADDR(CBREAK_STAUTS)
#define P_CDB_ADDR_REG CBUS_REG_ADDR(CDB_ADDR_REG)
#define P_CDB_DATA_REG CBUS_REG_ADDR(CDB_DATA_REG)
#define P_CDB_CTRL CBUS_REG_ADDR(CDB_CTRL)
#define P_CSFTINT0 CBUS_REG_ADDR(CSFTINT0)
#define P_CSFTINT1 CBUS_REG_ADDR(CSFTINT1)
#define P_IMEM_DMA_CTRL CBUS_REG_ADDR(IMEM_DMA_CTRL)
#define P_IMEM_DMA_ADR CBUS_REG_ADDR(IMEM_DMA_ADR)
#define P_IMEM_DMA_COUNT CBUS_REG_ADDR(IMEM_DMA_COUNT)
#define P_WRRSP_IMEM CBUS_REG_ADDR(WRRSP_IMEM)
#define P_LMEM_DMA_CTRL CBUS_REG_ADDR(LMEM_DMA_CTRL)
#define P_LMEM_DMA_ADR CBUS_REG_ADDR(LMEM_DMA_ADR)
#define P_LMEM_DMA_COUNT CBUS_REG_ADDR(LMEM_DMA_COUNT)
#define P_WRRSP_LMEM CBUS_REG_ADDR(WRRSP_LMEM)
#define P_MAC_CTRL1 CBUS_REG_ADDR(MAC_CTRL1)
#define P_ACC0REG1 CBUS_REG_ADDR(ACC0REG1)
#define P_ACC1REG1 CBUS_REG_ADDR(ACC1REG1)
#define P_MAC_CTRL2 CBUS_REG_ADDR(MAC_CTRL2)
#define P_ACC0REG2 CBUS_REG_ADDR(ACC0REG2)
#define P_ACC1REG2 CBUS_REG_ADDR(ACC1REG2)
#define P_CPU_TRACE CBUS_REG_ADDR(CPU_TRACE)
#define P_X_INT_ADR CBUS_REG_ADDR(X_INT_ADR)
#define P_GPIO_ADR CBUS_REG_ADDR(GPIO_ADR)
#define P_GPIO_ADR_H8 CBUS_REG_ADDR(GPIO_ADR_H8)
#define P_WFIFO_DEPTH CBUS_REG_ADDR(WFIFO_DEPTH)
#define P_WFIFO_PointerWidth CBUS_REG_ADDR(WFIFO_PointerWidth)
#define P_WFIFO_WORDSIZE CBUS_REG_ADDR(WFIFO_WORDSIZE)
#define P_CLR_ACC_MAC CBUS_REG_ADDR(CLR_ACC_MAC)
#define P_CLR_ACC_MAC2 CBUS_REG_ADDR(CLR_ACC_MAC2)
#define P_ACC_0 CBUS_REG_ADDR(ACC_0)
#define P_ACC_1 CBUS_REG_ADDR(ACC_1)
#define P_ACC_2 CBUS_REG_ADDR(ACC_2)
#define P_ACC_3 CBUS_REG_ADDR(ACC_3)
#define P_AIU_958_BPF CBUS_REG_ADDR(AIU_958_BPF)
#define P_AIU_958_BRST CBUS_REG_ADDR(AIU_958_BRST)
#define P_AIU_958_LENGTH CBUS_REG_ADDR(AIU_958_LENGTH)
#define P_AIU_958_PADDSIZE CBUS_REG_ADDR(AIU_958_PADDSIZE)
#define P_AIU_958_MISC CBUS_REG_ADDR(AIU_958_MISC)
#define P_AIU_958_FORCE_LEFT CBUS_REG_ADDR(AIU_958_FORCE_LEFT)
#define P_AIU_958_DISCARD_NUM CBUS_REG_ADDR(AIU_958_DISCARD_NUM)
#define P_AIU_958_DCU_FF_CTRL CBUS_REG_ADDR(AIU_958_DCU_FF_CTRL)
#define P_AIU_958_CHSTAT_L0 CBUS_REG_ADDR(AIU_958_CHSTAT_L0)
#define P_AIU_958_CHSTAT_L1 CBUS_REG_ADDR(AIU_958_CHSTAT_L1)
#define P_AIU_958_CTRL CBUS_REG_ADDR(AIU_958_CTRL)
#define P_AIU_958_RPT CBUS_REG_ADDR(AIU_958_RPT)
#define P_AIU_I2S_MUTE_SWAP CBUS_REG_ADDR(AIU_I2S_MUTE_SWAP)
#define P_AIU_I2S_SOURCE_DESC CBUS_REG_ADDR(AIU_I2S_SOURCE_DESC)
#define P_AIU_I2S_MED_CTRL CBUS_REG_ADDR(AIU_I2S_MED_CTRL)
#define P_AIU_I2S_MED_THRESH CBUS_REG_ADDR(AIU_I2S_MED_THRESH)
#define P_AIU_I2S_DAC_CFG CBUS_REG_ADDR(AIU_I2S_DAC_CFG)
#define P_AIU_I2S_SYNC CBUS_REG_ADDR(AIU_I2S_SYNC)
#define P_AIU_I2S_MISC CBUS_REG_ADDR(AIU_I2S_MISC)
#define P_AIU_I2S_OUT_CFG CBUS_REG_ADDR(AIU_I2S_OUT_CFG)
#define P_AIU_I2S_FF_CTRL CBUS_REG_ADDR(AIU_I2S_FF_CTRL)
#define P_AIU_RST_SOFT CBUS_REG_ADDR(AIU_RST_SOFT)
#define P_AIU_CLK_CTRL CBUS_REG_ADDR(AIU_CLK_CTRL)
#define P_AIU_MIX_ADCCFG CBUS_REG_ADDR(AIU_MIX_ADCCFG)
#define P_AIU_MIX_CTRL CBUS_REG_ADDR(AIU_MIX_CTRL)
#define P_AIU_CLK_CTRL_MORE CBUS_REG_ADDR(AIU_CLK_CTRL_MORE)
#define P_AIU_958_POP CBUS_REG_ADDR(AIU_958_POP)
#define P_AIU_MIX_GAIN CBUS_REG_ADDR(AIU_MIX_GAIN)
#define P_AIU_958_SYNWORD1 CBUS_REG_ADDR(AIU_958_SYNWORD1)
#define P_AIU_958_SYNWORD2 CBUS_REG_ADDR(AIU_958_SYNWORD2)
#define P_AIU_958_SYNWORD3 CBUS_REG_ADDR(AIU_958_SYNWORD3)
#define P_AIU_958_SYNWORD1_MASK CBUS_REG_ADDR(AIU_958_SYNWORD1_MASK)
#define P_AIU_958_SYNWORD2_MASK CBUS_REG_ADDR(AIU_958_SYNWORD2_MASK)
#define P_AIU_958_SYNWORD3_MASK CBUS_REG_ADDR(AIU_958_SYNWORD3_MASK)
#define P_AIU_958_FFRDOUT_THD CBUS_REG_ADDR(AIU_958_FFRDOUT_THD)
#define P_AIU_958_LENGTH_PER_PAUSE CBUS_REG_ADDR(AIU_958_LENGTH_PER_PAUSE)
#define P_AIU_958_PAUSE_NUM CBUS_REG_ADDR(AIU_958_PAUSE_NUM)
#define P_AIU_958_PAUSE_PAYLOAD CBUS_REG_ADDR(AIU_958_PAUSE_PAYLOAD)
#define P_AIU_958_AUTO_PAUSE CBUS_REG_ADDR(AIU_958_AUTO_PAUSE)
#define P_AIU_958_PAUSE_PD_LENGTH CBUS_REG_ADDR(AIU_958_PAUSE_PD_LENGTH)
#define P_AIU_958_CHSTAT_R0 CBUS_REG_ADDR(AIU_958_CHSTAT_R0)
#define P_AIU_958_CHSTAT_R1 CBUS_REG_ADDR(AIU_958_CHSTAT_R1)
#define P_AIU_958_VALID_CTRL CBUS_REG_ADDR(AIU_958_VALID_CTRL)
#define P_AIU_AUDIO_AMP_REG0 CBUS_REG_ADDR(AIU_AUDIO_AMP_REG0)
#define P_AIU_AUDIO_AMP_REG1 CBUS_REG_ADDR(AIU_AUDIO_AMP_REG1)
#define P_AIU_AUDIO_AMP_REG2 CBUS_REG_ADDR(AIU_AUDIO_AMP_REG2)
#define P_AIU_AUDIO_AMP_REG3 CBUS_REG_ADDR(AIU_AUDIO_AMP_REG3)
#define P_AIU_AIFIFO2_CTRL CBUS_REG_ADDR(AIU_AIFIFO2_CTRL)
#define P_AIU_AIFIFO2_STATUS CBUS_REG_ADDR(AIU_AIFIFO2_STATUS)
#define P_AIU_AIFIFO2_GBIT CBUS_REG_ADDR(AIU_AIFIFO2_GBIT)
#define P_AIU_AIFIFO2_CLB CBUS_REG_ADDR(AIU_AIFIFO2_CLB)
#define P_AIU_CRC_CTRL CBUS_REG_ADDR(AIU_CRC_CTRL)
#define P_AIU_CRC_STATUS CBUS_REG_ADDR(AIU_CRC_STATUS)
#define P_AIU_CRC_SHIFT_REG CBUS_REG_ADDR(AIU_CRC_SHIFT_REG)
#define P_AIU_CRC_IREG CBUS_REG_ADDR(AIU_CRC_IREG)
#define P_AIU_CRC_CAL_REG1 CBUS_REG_ADDR(AIU_CRC_CAL_REG1)
#define P_AIU_CRC_CAL_REG0 CBUS_REG_ADDR(AIU_CRC_CAL_REG0)
#define P_AIU_CRC_POLY_COEF1 CBUS_REG_ADDR(AIU_CRC_POLY_COEF1)
#define P_AIU_CRC_POLY_COEF0 CBUS_REG_ADDR(AIU_CRC_POLY_COEF0)
#define P_AIU_CRC_BIT_SIZE1 CBUS_REG_ADDR(AIU_CRC_BIT_SIZE1)
#define P_AIU_CRC_BIT_SIZE0 CBUS_REG_ADDR(AIU_CRC_BIT_SIZE0)
#define P_AIU_CRC_BIT_CNT1 CBUS_REG_ADDR(AIU_CRC_BIT_CNT1)
#define P_AIU_CRC_BIT_CNT0 CBUS_REG_ADDR(AIU_CRC_BIT_CNT0)
#define P_AIU_AMCLK_GATE_HI CBUS_REG_ADDR(AIU_AMCLK_GATE_HI)
#define P_AIU_AMCLK_GATE_LO CBUS_REG_ADDR(AIU_AMCLK_GATE_LO)
#define P_AIU_AMCLK_MSR CBUS_REG_ADDR(AIU_AMCLK_MSR)
#define P_AIU_AUDAC_CTRL0 CBUS_REG_ADDR(AIU_AUDAC_CTRL0)
#define P_AIU_AUDAC_CTRL1 CBUS_REG_ADDR(AIU_AUDAC_CTRL1)
#define P_AIU_DELTA_SIGMA0 CBUS_REG_ADDR(AIU_DELTA_SIGMA0)
#define P_AIU_DELTA_SIGMA1 CBUS_REG_ADDR(AIU_DELTA_SIGMA1)
#define P_AIU_DELTA_SIGMA2 CBUS_REG_ADDR(AIU_DELTA_SIGMA2)
#define P_AIU_DELTA_SIGMA3 CBUS_REG_ADDR(AIU_DELTA_SIGMA3)
#define P_AIU_DELTA_SIGMA4 CBUS_REG_ADDR(AIU_DELTA_SIGMA4)
#define P_AIU_DELTA_SIGMA5 CBUS_REG_ADDR(AIU_DELTA_SIGMA5)
#define P_AIU_DELTA_SIGMA6 CBUS_REG_ADDR(AIU_DELTA_SIGMA6)
#define P_AIU_DELTA_SIGMA7 CBUS_REG_ADDR(AIU_DELTA_SIGMA7)
#define P_AIU_DELTA_SIGMA_LCNTS CBUS_REG_ADDR(AIU_DELTA_SIGMA_LCNTS)
#define P_AIU_DELTA_SIGMA_RCNTS CBUS_REG_ADDR(AIU_DELTA_SIGMA_RCNTS)
#define P_AIU_MEM_I2S_START_PTR CBUS_REG_ADDR(AIU_MEM_I2S_START_PTR)
#define P_AIU_MEM_I2S_RD_PTR CBUS_REG_ADDR(AIU_MEM_I2S_RD_PTR)
#define P_AIU_MEM_I2S_END_PTR CBUS_REG_ADDR(AIU_MEM_I2S_END_PTR)
#define P_AIU_MEM_I2S_MASKS CBUS_REG_ADDR(AIU_MEM_I2S_MASKS)
#define P_AIU_MEM_I2S_CONTROL CBUS_REG_ADDR(AIU_MEM_I2S_CONTROL)
#define P_AIU_MEM_IEC958_START_PTR CBUS_REG_ADDR(AIU_MEM_IEC958_START_PTR)
#define P_AIU_MEM_IEC958_RD_PTR CBUS_REG_ADDR(AIU_MEM_IEC958_RD_PTR)
#define P_AIU_MEM_IEC958_END_PTR CBUS_REG_ADDR(AIU_MEM_IEC958_END_PTR)
#define P_AIU_MEM_IEC958_MASKS CBUS_REG_ADDR(AIU_MEM_IEC958_MASKS)
#define P_AIU_MEM_IEC958_CONTROL CBUS_REG_ADDR(AIU_MEM_IEC958_CONTROL)
#define P_AIU_MEM_AIFIFO2_START_PTR CBUS_REG_ADDR(AIU_MEM_AIFIFO2_START_PTR)
#define P_AIU_MEM_AIFIFO2_CURR_PTR CBUS_REG_ADDR(AIU_MEM_AIFIFO2_CURR_PTR)
#define P_AIU_MEM_AIFIFO2_END_PTR CBUS_REG_ADDR(AIU_MEM_AIFIFO2_END_PTR)
#define P_AIU_MEM_AIFIFO2_BYTES_AVAIL CBUS_REG_ADDR(AIU_MEM_AIFIFO2_BYTES_AVAIL)
#define P_AIU_MEM_AIFIFO2_CONTROL CBUS_REG_ADDR(AIU_MEM_AIFIFO2_CONTROL)
#define P_AIU_MEM_AIFIFO2_MAN_WP CBUS_REG_ADDR(AIU_MEM_AIFIFO2_MAN_WP)
#define P_AIU_MEM_AIFIFO2_MAN_RP CBUS_REG_ADDR(AIU_MEM_AIFIFO2_MAN_RP)
#define P_AIU_MEM_AIFIFO2_LEVEL CBUS_REG_ADDR(AIU_MEM_AIFIFO2_LEVEL)
#define P_AIU_MEM_AIFIFO2_BUF_CNTL CBUS_REG_ADDR(AIU_MEM_AIFIFO2_BUF_CNTL)
#define P_AIU_MEM_I2S_MAN_WP CBUS_REG_ADDR(AIU_MEM_I2S_MAN_WP)
#define P_AIU_MEM_I2S_MAN_RP CBUS_REG_ADDR(AIU_MEM_I2S_MAN_RP)
#define P_AIU_MEM_I2S_LEVEL CBUS_REG_ADDR(AIU_MEM_I2S_LEVEL)
#define P_AIU_MEM_I2S_BUF_CNTL CBUS_REG_ADDR(AIU_MEM_I2S_BUF_CNTL)
#define P_AIU_MEM_I2S_BUF_WRAP_COUNT CBUS_REG_ADDR(AIU_MEM_I2S_BUF_WRAP_COUNT)
#define P_AIU_MEM_I2S_MEM_CTL CBUS_REG_ADDR(AIU_MEM_I2S_MEM_CTL)
#define P_AIU_MEM_IEC958_MEM_CTL CBUS_REG_ADDR(AIU_MEM_IEC958_MEM_CTL)
#define P_AIU_MEM_IEC958_WRAP_COUNT CBUS_REG_ADDR(AIU_MEM_IEC958_WRAP_COUNT)
#define P_AIU_MEM_IEC958_IRQ_LEVEL CBUS_REG_ADDR(AIU_MEM_IEC958_IRQ_LEVEL)
#define P_AIU_MEM_IEC958_MAN_WP CBUS_REG_ADDR(AIU_MEM_IEC958_MAN_WP)
#define P_AIU_MEM_IEC958_MAN_RP CBUS_REG_ADDR(AIU_MEM_IEC958_MAN_RP)
#define P_AIU_MEM_IEC958_LEVEL CBUS_REG_ADDR(AIU_MEM_IEC958_LEVEL)
#define P_AIU_MEM_IEC958_BUF_CNTL CBUS_REG_ADDR(AIU_MEM_IEC958_BUF_CNTL)
#define P_AIU_AIFIFO_CTRL CBUS_REG_ADDR(AIU_AIFIFO_CTRL)
#define P_AIU_AIFIFO_STATUS CBUS_REG_ADDR(AIU_AIFIFO_STATUS)
#define P_AIU_AIFIFO_GBIT CBUS_REG_ADDR(AIU_AIFIFO_GBIT)
#define P_AIU_AIFIFO_CLB CBUS_REG_ADDR(AIU_AIFIFO_CLB)
#define P_AIU_MEM_AIFIFO_START_PTR CBUS_REG_ADDR(AIU_MEM_AIFIFO_START_PTR)
#define P_AIU_MEM_AIFIFO_CURR_PTR CBUS_REG_ADDR(AIU_MEM_AIFIFO_CURR_PTR)
#define P_AIU_MEM_AIFIFO_END_PTR CBUS_REG_ADDR(AIU_MEM_AIFIFO_END_PTR)
#define P_AIU_MEM_AIFIFO_BYTES_AVAIL CBUS_REG_ADDR(AIU_MEM_AIFIFO_BYTES_AVAIL)
#define P_AIU_MEM_AIFIFO_CONTROL CBUS_REG_ADDR(AIU_MEM_AIFIFO_CONTROL)
#define P_AIU_MEM_AIFIFO_MAN_WP CBUS_REG_ADDR(AIU_MEM_AIFIFO_MAN_WP)
#define P_AIU_MEM_AIFIFO_MAN_RP CBUS_REG_ADDR(AIU_MEM_AIFIFO_MAN_RP)
#define P_AIU_MEM_AIFIFO_LEVEL CBUS_REG_ADDR(AIU_MEM_AIFIFO_LEVEL)
#define P_AIU_MEM_AIFIFO_BUF_CNTL CBUS_REG_ADDR(AIU_MEM_AIFIFO_BUF_CNTL)
#define P_AIU_MEM_AIFIFO_BUF_WRAP_COUNT CBUS_REG_ADDR(AIU_MEM_AIFIFO_BUF_WRAP_COUNT)
#define P_AIU_MEM_AIFIFO2_BUF_WRAP_COUNT CBUS_REG_ADDR(AIU_MEM_AIFIFO2_BUF_WRAP_COUNT)
#define P_AIU_MEM_AIFIFO_MEM_CTL CBUS_REG_ADDR(AIU_MEM_AIFIFO_MEM_CTL)
#define P_AIFIFO_TIME_STAMP_CNTL CBUS_REG_ADDR(AIFIFO_TIME_STAMP_CNTL)
#define P_AIFIFO_TIME_STAMP_SYNC_0 CBUS_REG_ADDR(AIFIFO_TIME_STAMP_SYNC_0)
#define P_AIFIFO_TIME_STAMP_SYNC_1 CBUS_REG_ADDR(AIFIFO_TIME_STAMP_SYNC_1)
#define P_AIFIFO_TIME_STAMP_0 CBUS_REG_ADDR(AIFIFO_TIME_STAMP_0)
#define P_AIFIFO_TIME_STAMP_1 CBUS_REG_ADDR(AIFIFO_TIME_STAMP_1)
#define P_AIFIFO_TIME_STAMP_2 CBUS_REG_ADDR(AIFIFO_TIME_STAMP_2)
#define P_AIFIFO_TIME_STAMP_3 CBUS_REG_ADDR(AIFIFO_TIME_STAMP_3)
#define P_AIFIFO_TIME_STAMP_LENGTH CBUS_REG_ADDR(AIFIFO_TIME_STAMP_LENGTH)
#define P_AIFIFO2_TIME_STAMP_CNTL CBUS_REG_ADDR(AIFIFO2_TIME_STAMP_CNTL)
#define P_AIFIFO2_TIME_STAMP_SYNC_0 CBUS_REG_ADDR(AIFIFO2_TIME_STAMP_SYNC_0)
#define P_AIFIFO2_TIME_STAMP_SYNC_1 CBUS_REG_ADDR(AIFIFO2_TIME_STAMP_SYNC_1)
#define P_AIFIFO2_TIME_STAMP_0 CBUS_REG_ADDR(AIFIFO2_TIME_STAMP_0)
#define P_AIFIFO2_TIME_STAMP_1 CBUS_REG_ADDR(AIFIFO2_TIME_STAMP_1)
#define P_AIFIFO2_TIME_STAMP_2 CBUS_REG_ADDR(AIFIFO2_TIME_STAMP_2)
#define P_AIFIFO2_TIME_STAMP_3 CBUS_REG_ADDR(AIFIFO2_TIME_STAMP_3)
#define P_AIFIFO2_TIME_STAMP_LENGTH CBUS_REG_ADDR(AIFIFO2_TIME_STAMP_LENGTH)
#define P_IEC958_TIME_STAMP_CNTL CBUS_REG_ADDR(IEC958_TIME_STAMP_CNTL)
#define P_IEC958_TIME_STAMP_SYNC_0 CBUS_REG_ADDR(IEC958_TIME_STAMP_SYNC_0)
#define P_IEC958_TIME_STAMP_SYNC_1 CBUS_REG_ADDR(IEC958_TIME_STAMP_SYNC_1)
#define P_IEC958_TIME_STAMP_0 CBUS_REG_ADDR(IEC958_TIME_STAMP_0)
#define P_IEC958_TIME_STAMP_1 CBUS_REG_ADDR(IEC958_TIME_STAMP_1)
#define P_IEC958_TIME_STAMP_2 CBUS_REG_ADDR(IEC958_TIME_STAMP_2)
#define P_IEC958_TIME_STAMP_3 CBUS_REG_ADDR(IEC958_TIME_STAMP_3)
#define P_IEC958_TIME_STAMP_LENGTH CBUS_REG_ADDR(IEC958_TIME_STAMP_LENGTH)
#define P_AIU_MEM_AIFIFO2_MEM_CTL CBUS_REG_ADDR(AIU_MEM_AIFIFO2_MEM_CTL)
#define P_AIADR CBUS_REG_ADDR(AIADR)
#define P_AICSR CBUS_REG_ADDR(AICSR)
#define P_AIDAT CBUS_REG_ADDR(AIDAT)
#define P_AIGBIT CBUS_REG_ADDR(AIGBIT)
#define P_AICLB CBUS_REG_ADDR(AICLB)
#define P_HD0 CBUS_REG_ADDR(HD0)
#define P_HD1 CBUS_REG_ADDR(HD1)
#define P_SHD0 CBUS_REG_ADDR(SHD0)
#define P_SHD1 CBUS_REG_ADDR(SHD1)
#define P_SYND CBUS_REG_ADDR(SYND)
#define P_ECDCT CBUS_REG_ADDR(ECDCT)
#define P_ECDSTAT CBUS_REG_ADDR(ECDSTAT)
#define P_CTR0 CBUS_REG_ADDR(CTR0)
#define P_CTR1 CBUS_REG_ADDR(CTR1)
#define P_CTR2 CBUS_REG_ADDR(CTR2)
#define P_STAT0 CBUS_REG_ADDR(STAT0)
#define P_INT CBUS_REG_ADDR(INT)
#define P_TCTR0 CBUS_REG_ADDR(TCTR0)
#define P_TSTAT0 CBUS_REG_ADDR(TSTAT0)
#define P_TSTAT1 CBUS_REG_ADDR(TSTAT1)
#define P_VPP_DUMMY_DATA CBUS_REG_ADDR(VPP_DUMMY_DATA)
#define P_VPP_LINE_IN_LENGTH CBUS_REG_ADDR(VPP_LINE_IN_LENGTH)
#define P_VPP_PIC_IN_HEIGHT CBUS_REG_ADDR(VPP_PIC_IN_HEIGHT)
#define P_VPP_SCALE_COEF_IDX CBUS_REG_ADDR(VPP_SCALE_COEF_IDX)
#define P_VPP_SCALE_COEF CBUS_REG_ADDR(VPP_SCALE_COEF)
#define P_VPP_VSC_REGION12_STARTP CBUS_REG_ADDR(VPP_VSC_REGION12_STARTP)
#define P_VPP_VSC_REGION34_STARTP CBUS_REG_ADDR(VPP_VSC_REGION34_STARTP)
#define P_VPP_VSC_REGION4_ENDP CBUS_REG_ADDR(VPP_VSC_REGION4_ENDP)
#define P_VPP_VSC_START_PHASE_STEP CBUS_REG_ADDR(VPP_VSC_START_PHASE_STEP)
#define P_VPP_VSC_REGION0_PHASE_SLOPE CBUS_REG_ADDR(VPP_VSC_REGION0_PHASE_SLOPE)
#define P_VPP_VSC_REGION1_PHASE_SLOPE CBUS_REG_ADDR(VPP_VSC_REGION1_PHASE_SLOPE)
#define P_VPP_VSC_REGION3_PHASE_SLOPE CBUS_REG_ADDR(VPP_VSC_REGION3_PHASE_SLOPE)
#define P_VPP_VSC_REGION4_PHASE_SLOPE CBUS_REG_ADDR(VPP_VSC_REGION4_PHASE_SLOPE)
#define P_VPP_VSC_PHASE_CTRL CBUS_REG_ADDR(VPP_VSC_PHASE_CTRL)
#define P_VPP_VSC_INI_PHASE CBUS_REG_ADDR(VPP_VSC_INI_PHASE)
#define P_VPP_HSC_REGION12_STARTP CBUS_REG_ADDR(VPP_HSC_REGION12_STARTP)
#define P_VPP_HSC_REGION34_STARTP CBUS_REG_ADDR(VPP_HSC_REGION34_STARTP)
#define P_VPP_HSC_REGION4_ENDP CBUS_REG_ADDR(VPP_HSC_REGION4_ENDP)
#define P_VPP_HSC_START_PHASE_STEP CBUS_REG_ADDR(VPP_HSC_START_PHASE_STEP)
#define P_VPP_HSC_REGION0_PHASE_SLOPE CBUS_REG_ADDR(VPP_HSC_REGION0_PHASE_SLOPE)
#define P_VPP_HSC_REGION1_PHASE_SLOPE CBUS_REG_ADDR(VPP_HSC_REGION1_PHASE_SLOPE)
#define P_VPP_HSC_REGION3_PHASE_SLOPE CBUS_REG_ADDR(VPP_HSC_REGION3_PHASE_SLOPE)
#define P_VPP_HSC_REGION4_PHASE_SLOPE CBUS_REG_ADDR(VPP_HSC_REGION4_PHASE_SLOPE)
#define P_VPP_HSC_PHASE_CTRL CBUS_REG_ADDR(VPP_HSC_PHASE_CTRL)
#define P_VPP_SC_MISC CBUS_REG_ADDR(VPP_SC_MISC)
#define P_VPP_PREBLEND_VD1_H_START_END CBUS_REG_ADDR(VPP_PREBLEND_VD1_H_START_END)
#define P_VPP_PREBLEND_VD1_V_START_END CBUS_REG_ADDR(VPP_PREBLEND_VD1_V_START_END)
#define P_VPP_POSTBLEND_VD1_H_START_END CBUS_REG_ADDR(VPP_POSTBLEND_VD1_H_START_END)
#define P_VPP_POSTBLEND_VD1_V_START_END CBUS_REG_ADDR(VPP_POSTBLEND_VD1_V_START_END)
#define P_VPP_BLEND_VD2_H_START_END CBUS_REG_ADDR(VPP_BLEND_VD2_H_START_END)
#define P_VPP_BLEND_VD2_V_START_END CBUS_REG_ADDR(VPP_BLEND_VD2_V_START_END)
#define P_VPP_PREBLEND_H_SIZE CBUS_REG_ADDR(VPP_PREBLEND_H_SIZE)
#define P_VPP_POSTBLEND_H_SIZE CBUS_REG_ADDR(VPP_POSTBLEND_H_SIZE)
#define P_VPP_HOLD_LINES CBUS_REG_ADDR(VPP_HOLD_LINES)
#define P_VPP_BLEND_ONECOLOR_CTRL CBUS_REG_ADDR(VPP_BLEND_ONECOLOR_CTRL)
#define P_VPP_PREBLEND_CURRENT_XY CBUS_REG_ADDR(VPP_PREBLEND_CURRENT_XY)
#define P_VPP_POSTBLEND_CURRENT_XY CBUS_REG_ADDR(VPP_POSTBLEND_CURRENT_XY)
#define P_VPP_MISC CBUS_REG_ADDR(VPP_MISC)
#define P_VPP_OFIFO_SIZE CBUS_REG_ADDR(VPP_OFIFO_SIZE)
#define P_VPP_FIFO_STATUS CBUS_REG_ADDR(VPP_FIFO_STATUS)
#define P_VPP_SMOKE_CTRL CBUS_REG_ADDR(VPP_SMOKE_CTRL)
#define P_VPP_SMOKE1_VAL CBUS_REG_ADDR(VPP_SMOKE1_VAL)
#define P_VPP_SMOKE2_VAL CBUS_REG_ADDR(VPP_SMOKE2_VAL)
#define P_VPP_SMOKE3_VAL CBUS_REG_ADDR(VPP_SMOKE3_VAL)
#define P_VPP_SMOKE1_H_START_END CBUS_REG_ADDR(VPP_SMOKE1_H_START_END)
#define P_VPP_SMOKE1_V_START_END CBUS_REG_ADDR(VPP_SMOKE1_V_START_END)
#define P_VPP_SMOKE2_H_START_END CBUS_REG_ADDR(VPP_SMOKE2_H_START_END)
#define P_VPP_SMOKE2_V_START_END CBUS_REG_ADDR(VPP_SMOKE2_V_START_END)
#define P_VPP_SMOKE3_H_START_END CBUS_REG_ADDR(VPP_SMOKE3_H_START_END)
#define P_VPP_SMOKE3_V_START_END CBUS_REG_ADDR(VPP_SMOKE3_V_START_END)
#define P_VPP_SCO_FIFO_CTRL CBUS_REG_ADDR(VPP_SCO_FIFO_CTRL)
#define P_VPP_VADJ_CTRL CBUS_REG_ADDR(VPP_VADJ_CTRL)
#define P_VPP_VADJ1_Y CBUS_REG_ADDR(VPP_VADJ1_Y)
#define P_VPP_VADJ1_MA_MB CBUS_REG_ADDR(VPP_VADJ1_MA_MB)
#define P_VPP_VADJ1_MC_MD CBUS_REG_ADDR(VPP_VADJ1_MC_MD)
#define P_VPP_VADJ2_Y CBUS_REG_ADDR(VPP_VADJ2_Y)
#define P_VPP_VADJ2_MA_MB CBUS_REG_ADDR(VPP_VADJ2_MA_MB)
#define P_VPP_VADJ2_MC_MD CBUS_REG_ADDR(VPP_VADJ2_MC_MD)
#define P_VPP_HSHARP_CTRL CBUS_REG_ADDR(VPP_HSHARP_CTRL)
#define P_VPP_HSHARP_LUMA_THRESH01 CBUS_REG_ADDR(VPP_HSHARP_LUMA_THRESH01)
#define P_VPP_HSHARP_LUMA_THRESH23 CBUS_REG_ADDR(VPP_HSHARP_LUMA_THRESH23)
#define P_VPP_HSHARP_CHROMA_THRESH01 CBUS_REG_ADDR(VPP_HSHARP_CHROMA_THRESH01)
#define P_VPP_HSHARP_CHROMA_THRESH23 CBUS_REG_ADDR(VPP_HSHARP_CHROMA_THRESH23)
#define P_VPP_HSHARP_LUMA_GAIN CBUS_REG_ADDR(VPP_HSHARP_LUMA_GAIN)
#define P_VPP_HSHARP_CHROMA_GAIN CBUS_REG_ADDR(VPP_HSHARP_CHROMA_GAIN)
#define P_VPP_MATRIX_CTRL CBUS_REG_ADDR(VPP_MATRIX_CTRL)
#define P_VPP_MATRIX_COEF00_01 CBUS_REG_ADDR(VPP_MATRIX_COEF00_01)
#define P_VPP_MATRIX_COEF02_10 CBUS_REG_ADDR(VPP_MATRIX_COEF02_10)
#define P_VPP_MATRIX_COEF11_12 CBUS_REG_ADDR(VPP_MATRIX_COEF11_12)
#define P_VPP_MATRIX_COEF20_21 CBUS_REG_ADDR(VPP_MATRIX_COEF20_21)
#define P_VPP_MATRIX_COEF22 CBUS_REG_ADDR(VPP_MATRIX_COEF22)
#define P_VPP_MATRIX_OFFSET0_1 CBUS_REG_ADDR(VPP_MATRIX_OFFSET0_1)
#define P_VPP_MATRIX_OFFSET2 CBUS_REG_ADDR(VPP_MATRIX_OFFSET2)
#define P_VPP_MATRIX_PRE_OFFSET0_1 CBUS_REG_ADDR(VPP_MATRIX_PRE_OFFSET0_1)
#define P_VPP_MATRIX_PRE_OFFSET2 CBUS_REG_ADDR(VPP_MATRIX_PRE_OFFSET2)
#define P_VPP_DUMMY_DATA1 CBUS_REG_ADDR(VPP_DUMMY_DATA1)
#define P_VPP_GAINOFF_CTRL0 CBUS_REG_ADDR(VPP_GAINOFF_CTRL0)
#define P_VPP_GAINOFF_CTRL1 CBUS_REG_ADDR(VPP_GAINOFF_CTRL1)
#define P_VPP_GAINOFF_CTRL2 CBUS_REG_ADDR(VPP_GAINOFF_CTRL2)
#define P_VPP_GAINOFF_CTRL3 CBUS_REG_ADDR(VPP_GAINOFF_CTRL3)
#define P_VPP_GAINOFF_CTRL4 CBUS_REG_ADDR(VPP_GAINOFF_CTRL4)
#define P_VPP_CHROMA_ADDR_PORT CBUS_REG_ADDR(VPP_CHROMA_ADDR_PORT)
#define P_VPP_CHROMA_DATA_PORT CBUS_REG_ADDR(VPP_CHROMA_DATA_PORT)
#define P_CHROMA_GAIN_REG00 CBUS_REG_ADDR(CHROMA_GAIN_REG00)
#define P_HUE_HUE_RANGE_REG00 CBUS_REG_ADDR(HUE_HUE_RANGE_REG00)
#define P_HUE_RANGE_INV_REG00 CBUS_REG_ADDR(HUE_RANGE_INV_REG00)
#define P_HUE_LUM_RANGE_REG00 CBUS_REG_ADDR(HUE_LUM_RANGE_REG00)
#define P_HUE_SAT_RANGE_REG00 CBUS_REG_ADDR(HUE_SAT_RANGE_REG00)
#define P_SAT_SAT_RANGE_REG00 CBUS_REG_ADDR(SAT_SAT_RANGE_REG00)
#define P_CHROMA_GAIN_REG01 CBUS_REG_ADDR(CHROMA_GAIN_REG01)
#define P_HUE_HUE_RANGE_REG01 CBUS_REG_ADDR(HUE_HUE_RANGE_REG01)
#define P_HUE_RANGE_INV_REG01 CBUS_REG_ADDR(HUE_RANGE_INV_REG01)
#define P_HUE_LUM_RANGE_REG01 CBUS_REG_ADDR(HUE_LUM_RANGE_REG01)
#define P_HUE_SAT_RANGE_REG01 CBUS_REG_ADDR(HUE_SAT_RANGE_REG01)
#define P_SAT_SAT_RANGE_REG01 CBUS_REG_ADDR(SAT_SAT_RANGE_REG01)
#define P_CHROMA_GAIN_REG02 CBUS_REG_ADDR(CHROMA_GAIN_REG02)
#define P_HUE_HUE_RANGE_REG02 CBUS_REG_ADDR(HUE_HUE_RANGE_REG02)
#define P_HUE_RANGE_INV_REG02 CBUS_REG_ADDR(HUE_RANGE_INV_REG02)
#define P_HUE_LUM_RANGE_REG02 CBUS_REG_ADDR(HUE_LUM_RANGE_REG02)
#define P_HUE_SAT_RANGE_REG02 CBUS_REG_ADDR(HUE_SAT_RANGE_REG02)
#define P_SAT_SAT_RANGE_REG02 CBUS_REG_ADDR(SAT_SAT_RANGE_REG02)
#define P_CHROMA_GAIN_REG03 CBUS_REG_ADDR(CHROMA_GAIN_REG03)
#define P_HUE_HUE_RANGE_REG03 CBUS_REG_ADDR(HUE_HUE_RANGE_REG03)
#define P_HUE_RANGE_INV_REG03 CBUS_REG_ADDR(HUE_RANGE_INV_REG03)
#define P_HUE_LUM_RANGE_REG03 CBUS_REG_ADDR(HUE_LUM_RANGE_REG03)
#define P_HUE_SAT_RANGE_REG03 CBUS_REG_ADDR(HUE_SAT_RANGE_REG03)
#define P_SAT_SAT_RANGE_REG03 CBUS_REG_ADDR(SAT_SAT_RANGE_REG03)
#define P_CHROMA_GAIN_REG04 CBUS_REG_ADDR(CHROMA_GAIN_REG04)
#define P_HUE_HUE_RANGE_REG04 CBUS_REG_ADDR(HUE_HUE_RANGE_REG04)
#define P_HUE_RANGE_INV_REG04 CBUS_REG_ADDR(HUE_RANGE_INV_REG04)
#define P_HUE_LUM_RANGE_REG04 CBUS_REG_ADDR(HUE_LUM_RANGE_REG04)
#define P_HUE_SAT_RANGE_REG04 CBUS_REG_ADDR(HUE_SAT_RANGE_REG04)
#define P_SAT_SAT_RANGE_REG04 CBUS_REG_ADDR(SAT_SAT_RANGE_REG04)
#define P_CHROMA_GAIN_REG05 CBUS_REG_ADDR(CHROMA_GAIN_REG05)
#define P_HUE_HUE_RANGE_REG05 CBUS_REG_ADDR(HUE_HUE_RANGE_REG05)
#define P_HUE_RANGE_INV_REG05 CBUS_REG_ADDR(HUE_RANGE_INV_REG05)
#define P_HUE_LUM_RANGE_REG05 CBUS_REG_ADDR(HUE_LUM_RANGE_REG05)
#define P_HUE_SAT_RANGE_REG05 CBUS_REG_ADDR(HUE_SAT_RANGE_REG05)
#define P_SAT_SAT_RANGE_REG05 CBUS_REG_ADDR(SAT_SAT_RANGE_REG05)
#define P_CHROMA_GAIN_REG06 CBUS_REG_ADDR(CHROMA_GAIN_REG06)
#define P_HUE_HUE_RANGE_REG06 CBUS_REG_ADDR(HUE_HUE_RANGE_REG06)
#define P_HUE_RANGE_INV_REG06 CBUS_REG_ADDR(HUE_RANGE_INV_REG06)
#define P_HUE_LUM_RANGE_REG06 CBUS_REG_ADDR(HUE_LUM_RANGE_REG06)
#define P_HUE_SAT_RANGE_REG06 CBUS_REG_ADDR(HUE_SAT_RANGE_REG06)
#define P_SAT_SAT_RANGE_REG06 CBUS_REG_ADDR(SAT_SAT_RANGE_REG06)
#define P_CHROMA_GAIN_REG07 CBUS_REG_ADDR(CHROMA_GAIN_REG07)
#define P_HUE_HUE_RANGE_REG07 CBUS_REG_ADDR(HUE_HUE_RANGE_REG07)
#define P_HUE_RANGE_INV_REG07 CBUS_REG_ADDR(HUE_RANGE_INV_REG07)
#define P_HUE_LUM_RANGE_REG07 CBUS_REG_ADDR(HUE_LUM_RANGE_REG07)
#define P_HUE_SAT_RANGE_REG07 CBUS_REG_ADDR(HUE_SAT_RANGE_REG07)
#define P_SAT_SAT_RANGE_REG07 CBUS_REG_ADDR(SAT_SAT_RANGE_REG07)
#define P_REG_CHROMA_CONTROL CBUS_REG_ADDR(REG_CHROMA_CONTROL)
#define P_VPP_GCLK_CTRL0 CBUS_REG_ADDR(VPP_GCLK_CTRL0)
#define P_VPP_GCLK_CTRL1 CBUS_REG_ADDR(VPP_GCLK_CTRL1)
#define P_VPP_SC_GCLK_CTRL CBUS_REG_ADDR(VPP_SC_GCLK_CTRL)
#define P_VPP_BLACKEXT_CTRL CBUS_REG_ADDR(VPP_BLACKEXT_CTRL)
#define P_VPP_DNLP_CTRL_00 CBUS_REG_ADDR(VPP_DNLP_CTRL_00)
#define P_VPP_DNLP_CTRL_01 CBUS_REG_ADDR(VPP_DNLP_CTRL_01)
#define P_VPP_DNLP_CTRL_02 CBUS_REG_ADDR(VPP_DNLP_CTRL_02)
#define P_VPP_DNLP_CTRL_03 CBUS_REG_ADDR(VPP_DNLP_CTRL_03)
#define P_VPP_DNLP_CTRL_04 CBUS_REG_ADDR(VPP_DNLP_CTRL_04)
#define P_VPP_DNLP_CTRL_05 CBUS_REG_ADDR(VPP_DNLP_CTRL_05)
#define P_VPP_DNLP_CTRL_06 CBUS_REG_ADDR(VPP_DNLP_CTRL_06)
#define P_VPP_DNLP_CTRL_07 CBUS_REG_ADDR(VPP_DNLP_CTRL_07)
#define P_VPP_DNLP_CTRL_08 CBUS_REG_ADDR(VPP_DNLP_CTRL_08)
#define P_VPP_DNLP_CTRL_09 CBUS_REG_ADDR(VPP_DNLP_CTRL_09)
#define P_VPP_DNLP_CTRL_10 CBUS_REG_ADDR(VPP_DNLP_CTRL_10)
#define P_VPP_DNLP_CTRL_11 CBUS_REG_ADDR(VPP_DNLP_CTRL_11)
#define P_VPP_DNLP_CTRL_12 CBUS_REG_ADDR(VPP_DNLP_CTRL_12)
#define P_VPP_DNLP_CTRL_13 CBUS_REG_ADDR(VPP_DNLP_CTRL_13)
#define P_VPP_DNLP_CTRL_14 CBUS_REG_ADDR(VPP_DNLP_CTRL_14)
#define P_VPP_DNLP_CTRL_15 CBUS_REG_ADDR(VPP_DNLP_CTRL_15)
#define P_VPP_PEAKING_HGAIN CBUS_REG_ADDR(VPP_PEAKING_HGAIN)
#define P_VPP_PEAKING_VGAIN CBUS_REG_ADDR(VPP_PEAKING_VGAIN)
#define P_VPP_PEAKING_NLP_1 CBUS_REG_ADDR(VPP_PEAKING_NLP_1)
#define P_VPP_PEAKING_NLP_2 CBUS_REG_ADDR(VPP_PEAKING_NLP_2)
#define P_VPP_PEAKING_NLP_3 CBUS_REG_ADDR(VPP_PEAKING_NLP_3)
#define P_VPP_PEAKING_NLP_4 CBUS_REG_ADDR(VPP_PEAKING_NLP_4)
#define P_VPP_PEAKING_NLP_5 CBUS_REG_ADDR(VPP_PEAKING_NLP_5)
#define P_VPP_SHARP_LIMIT CBUS_REG_ADDR(VPP_SHARP_LIMIT)
#define P_VPP_VLTI_CTRL CBUS_REG_ADDR(VPP_VLTI_CTRL)
#define P_VPP_HLTI_CTRL CBUS_REG_ADDR(VPP_HLTI_CTRL)
#define P_VPP_CTI_CTRL CBUS_REG_ADDR(VPP_CTI_CTRL)
#define P_VPP_BLUE_STRETCH_1 CBUS_REG_ADDR(VPP_BLUE_STRETCH_1)
#define P_VPP_BLUE_STRETCH_2 CBUS_REG_ADDR(VPP_BLUE_STRETCH_2)
#define P_VPP_BLUE_STRETCH_3 CBUS_REG_ADDR(VPP_BLUE_STRETCH_3)
#define P_VPP_CCORING_CTRL CBUS_REG_ADDR(VPP_CCORING_CTRL)
#define P_VPP_VE_ENABLE_CTRL CBUS_REG_ADDR(VPP_VE_ENABLE_CTRL)
#define P_VPP_VE_DEMO_LEFT_SCREEN_WIDTH CBUS_REG_ADDR(VPP_VE_DEMO_LEFT_SCREEN_WIDTH)
#define P_GE2D_GEN_CTRL0 CBUS_REG_ADDR(GE2D_GEN_CTRL0)
#define P_GE2D_GEN_CTRL1 CBUS_REG_ADDR(GE2D_GEN_CTRL1)
#define P_GE2D_GEN_CTRL2 CBUS_REG_ADDR(GE2D_GEN_CTRL2)
#define P_GE2D_CMD_CTRL CBUS_REG_ADDR(GE2D_CMD_CTRL)
#define P_GE2D_STATUS0 CBUS_REG_ADDR(GE2D_STATUS0)
#define P_GE2D_STATUS1 CBUS_REG_ADDR(GE2D_STATUS1)
#define P_GE2D_SRC1_DEF_COLOR CBUS_REG_ADDR(GE2D_SRC1_DEF_COLOR)
#define P_GE2D_SRC1_CLIPX_START_END CBUS_REG_ADDR(GE2D_SRC1_CLIPX_START_END)
#define P_GE2D_SRC1_CLIPY_START_END CBUS_REG_ADDR(GE2D_SRC1_CLIPY_START_END)
#define P_GE2D_SRC1_CANVAS CBUS_REG_ADDR(GE2D_SRC1_CANVAS)
#define P_GE2D_SRC1_X_START_END CBUS_REG_ADDR(GE2D_SRC1_X_START_END)
#define P_GE2D_SRC1_Y_START_END CBUS_REG_ADDR(GE2D_SRC1_Y_START_END)
#define P_GE2D_SRC1_LUT_ADDR CBUS_REG_ADDR(GE2D_SRC1_LUT_ADDR)
#define P_GE2D_SRC1_LUT_DAT CBUS_REG_ADDR(GE2D_SRC1_LUT_DAT)
#define P_GE2D_SRC1_FMT_CTRL CBUS_REG_ADDR(GE2D_SRC1_FMT_CTRL)
#define P_GE2D_SRC2_DEF_COLOR CBUS_REG_ADDR(GE2D_SRC2_DEF_COLOR)
#define P_GE2D_SRC2_CLIPX_START_END CBUS_REG_ADDR(GE2D_SRC2_CLIPX_START_END)
#define P_GE2D_SRC2_CLIPY_START_END CBUS_REG_ADDR(GE2D_SRC2_CLIPY_START_END)
#define P_GE2D_SRC2_X_START_END CBUS_REG_ADDR(GE2D_SRC2_X_START_END)
#define P_GE2D_SRC2_Y_START_END CBUS_REG_ADDR(GE2D_SRC2_Y_START_END)
#define P_GE2D_DST_CLIPX_START_END CBUS_REG_ADDR(GE2D_DST_CLIPX_START_END)
#define P_GE2D_DST_CLIPY_START_END CBUS_REG_ADDR(GE2D_DST_CLIPY_START_END)
#define P_GE2D_DST_X_START_END CBUS_REG_ADDR(GE2D_DST_X_START_END)
#define P_GE2D_DST_Y_START_END CBUS_REG_ADDR(GE2D_DST_Y_START_END)
#define P_GE2D_SRC2_DST_CANVAS CBUS_REG_ADDR(GE2D_SRC2_DST_CANVAS)
#define P_GE2D_VSC_START_PHASE_STEP CBUS_REG_ADDR(GE2D_VSC_START_PHASE_STEP)
#define P_GE2D_VSC_PHASE_SLOPE CBUS_REG_ADDR(GE2D_VSC_PHASE_SLOPE)
#define P_GE2D_VSC_INI_CTRL CBUS_REG_ADDR(GE2D_VSC_INI_CTRL)
#define P_GE2D_HSC_START_PHASE_STEP CBUS_REG_ADDR(GE2D_HSC_START_PHASE_STEP)
#define P_GE2D_HSC_PHASE_SLOPE CBUS_REG_ADDR(GE2D_HSC_PHASE_SLOPE)
#define P_GE2D_HSC_INI_CTRL CBUS_REG_ADDR(GE2D_HSC_INI_CTRL)
#define P_GE2D_HSC_ADV_CTRL CBUS_REG_ADDR(GE2D_HSC_ADV_CTRL)
#define P_GE2D_SC_MISC_CTRL CBUS_REG_ADDR(GE2D_SC_MISC_CTRL)
#define P_GE2D_VSC_NRND_POINT CBUS_REG_ADDR(GE2D_VSC_NRND_POINT)
#define P_GE2D_VSC_NRND_PHASE CBUS_REG_ADDR(GE2D_VSC_NRND_PHASE)
#define P_GE2D_HSC_NRND_POINT CBUS_REG_ADDR(GE2D_HSC_NRND_POINT)
#define P_GE2D_HSC_NRND_PHASE CBUS_REG_ADDR(GE2D_HSC_NRND_PHASE)
#define P_GE2D_MATRIX_PRE_OFFSET CBUS_REG_ADDR(GE2D_MATRIX_PRE_OFFSET)
#define P_GE2D_MATRIX_COEF00_01 CBUS_REG_ADDR(GE2D_MATRIX_COEF00_01)
#define P_GE2D_MATRIX_COEF02_10 CBUS_REG_ADDR(GE2D_MATRIX_COEF02_10)
#define P_GE2D_MATRIX_COEF11_12 CBUS_REG_ADDR(GE2D_MATRIX_COEF11_12)
#define P_GE2D_MATRIX_COEF20_21 CBUS_REG_ADDR(GE2D_MATRIX_COEF20_21)
#define P_GE2D_MATRIX_COEF22_CTRL CBUS_REG_ADDR(GE2D_MATRIX_COEF22_CTRL)
#define P_GE2D_MATRIX_OFFSET CBUS_REG_ADDR(GE2D_MATRIX_OFFSET)
#define P_GE2D_ALU_OP_CTRL CBUS_REG_ADDR(GE2D_ALU_OP_CTRL)
#define P_GE2D_ALU_CONST_COLOR CBUS_REG_ADDR(GE2D_ALU_CONST_COLOR)
#define P_GE2D_SRC1_KEY CBUS_REG_ADDR(GE2D_SRC1_KEY)
#define P_GE2D_SRC1_KEY_MASK CBUS_REG_ADDR(GE2D_SRC1_KEY_MASK)
#define P_GE2D_SRC2_KEY CBUS_REG_ADDR(GE2D_SRC2_KEY)
#define P_GE2D_SRC2_KEY_MASK CBUS_REG_ADDR(GE2D_SRC2_KEY_MASK)
#define P_GE2D_DST_BITMASK CBUS_REG_ADDR(GE2D_DST_BITMASK)
#define P_GE2D_DP_ONOFF_CTRL CBUS_REG_ADDR(GE2D_DP_ONOFF_CTRL)
#define P_GE2D_SCALE_COEF_IDX CBUS_REG_ADDR(GE2D_SCALE_COEF_IDX)
#define P_GE2D_SCALE_COEF CBUS_REG_ADDR(GE2D_SCALE_COEF)
#define P_GE2D_SRC_OUTSIDE_ALPHA CBUS_REG_ADDR(GE2D_SRC_OUTSIDE_ALPHA)
#define P_GE2D_ANTIFLICK_CTRL0 CBUS_REG_ADDR(GE2D_ANTIFLICK_CTRL0)
#define P_GE2D_ANTIFLICK_CTRL1 CBUS_REG_ADDR(GE2D_ANTIFLICK_CTRL1)
#define P_GE2D_ANTIFLICK_COLOR_FILT0 CBUS_REG_ADDR(GE2D_ANTIFLICK_COLOR_FILT0)
#define P_GE2D_ANTIFLICK_COLOR_FILT1 CBUS_REG_ADDR(GE2D_ANTIFLICK_COLOR_FILT1)
#define P_GE2D_ANTIFLICK_COLOR_FILT2 CBUS_REG_ADDR(GE2D_ANTIFLICK_COLOR_FILT2)
#define P_GE2D_ANTIFLICK_COLOR_FILT3 CBUS_REG_ADDR(GE2D_ANTIFLICK_COLOR_FILT3)
#define P_GE2D_ANTIFLICK_ALPHA_FILT0 CBUS_REG_ADDR(GE2D_ANTIFLICK_ALPHA_FILT0)
#define P_GE2D_ANTIFLICK_ALPHA_FILT1 CBUS_REG_ADDR(GE2D_ANTIFLICK_ALPHA_FILT1)
#define P_GE2D_ANTIFLICK_ALPHA_FILT2 CBUS_REG_ADDR(GE2D_ANTIFLICK_ALPHA_FILT2)
#define P_GE2D_ANTIFLICK_ALPHA_FILT3 CBUS_REG_ADDR(GE2D_ANTIFLICK_ALPHA_FILT3)
#define P_GE2D_SRC1_RANGE_MAP_Y_CTRL CBUS_REG_ADDR(GE2D_SRC1_RANGE_MAP_Y_CTRL)
#define P_GE2D_SRC1_RANGE_MAP_CB_CTRL CBUS_REG_ADDR(GE2D_SRC1_RANGE_MAP_CB_CTRL)
#define P_GE2D_SRC1_RANGE_MAP_CR_CTRL CBUS_REG_ADDR(GE2D_SRC1_RANGE_MAP_CR_CTRL)
#define P_GE2D_ARB_BURST_NUM CBUS_REG_ADDR(GE2D_ARB_BURST_NUM)
#define P_GE2D_TID_TOKEN CBUS_REG_ADDR(GE2D_TID_TOKEN)
#define P_MC_CTRL_REG CBUS_REG_ADDR(MC_CTRL_REG)
#define P_MC_MB_INFO CBUS_REG_ADDR(MC_MB_INFO)
#define P_MC_PIC_INFO CBUS_REG_ADDR(MC_PIC_INFO)
#define P_MC_HALF_PEL_ONE CBUS_REG_ADDR(MC_HALF_PEL_ONE)
#define P_MC_HALF_PEL_TWO CBUS_REG_ADDR(MC_HALF_PEL_TWO)
#define P_POWER_CTL_MC CBUS_REG_ADDR(POWER_CTL_MC)
#define P_MC_CMD CBUS_REG_ADDR(MC_CMD)
#define P_MC_CTRL0 CBUS_REG_ADDR(MC_CTRL0)
#define P_MC_PIC_W_H CBUS_REG_ADDR(MC_PIC_W_H)
#define P_MC_STATUS0 CBUS_REG_ADDR(MC_STATUS0)
#define P_MC_STATUS1 CBUS_REG_ADDR(MC_STATUS1)
#define P_MC_CTRL1 CBUS_REG_ADDR(MC_CTRL1)
#define P_MC_MIX_RATIO0 CBUS_REG_ADDR(MC_MIX_RATIO0)
#define P_MC_MIX_RATIO1 CBUS_REG_ADDR(MC_MIX_RATIO1)
#define P_MC_DP_MB_XY CBUS_REG_ADDR(MC_DP_MB_XY)
#define P_MC_OM_MB_XY CBUS_REG_ADDR(MC_OM_MB_XY)
#define P_PSCALE_RST CBUS_REG_ADDR(PSCALE_RST)
#define P_PSCALE_CTRL CBUS_REG_ADDR(PSCALE_CTRL)
#define P_PSCALE_PICI_W CBUS_REG_ADDR(PSCALE_PICI_W)
#define P_PSCALE_PICI_H CBUS_REG_ADDR(PSCALE_PICI_H)
#define P_PSCALE_PICO_W CBUS_REG_ADDR(PSCALE_PICO_W)
#define P_PSCALE_PICO_H CBUS_REG_ADDR(PSCALE_PICO_H)
#define P_PSCALE_PICO_START_X CBUS_REG_ADDR(PSCALE_PICO_START_X)
#define P_PSCALE_PICO_START_Y CBUS_REG_ADDR(PSCALE_PICO_START_Y)
#define P_PSCALE_DUMMY CBUS_REG_ADDR(PSCALE_DUMMY)
#define P_PSCALE_FILT0_COEF0 CBUS_REG_ADDR(PSCALE_FILT0_COEF0)
#define P_PSCALE_FILT0_COEF1 CBUS_REG_ADDR(PSCALE_FILT0_COEF1)
#define P_PSCALE_CMD_CTRL CBUS_REG_ADDR(PSCALE_CMD_CTRL)
#define P_PSCALE_CMD_BLK_X CBUS_REG_ADDR(PSCALE_CMD_BLK_X)
#define P_PSCALE_CMD_BLK_Y CBUS_REG_ADDR(PSCALE_CMD_BLK_Y)
#define P_PSCALE_STATUS CBUS_REG_ADDR(PSCALE_STATUS)
#define P_PSCALE_BMEM_ADDR CBUS_REG_ADDR(PSCALE_BMEM_ADDR)
#define P_PSCALE_BMEM_DAT CBUS_REG_ADDR(PSCALE_BMEM_DAT)
#define P_PSCALE_DRAM_BUF_CTRL CBUS_REG_ADDR(PSCALE_DRAM_BUF_CTRL)
#define P_PSCALE_MCMD_CTRL CBUS_REG_ADDR(PSCALE_MCMD_CTRL)
#define P_PSCALE_MCMD_XSIZE CBUS_REG_ADDR(PSCALE_MCMD_XSIZE)
#define P_PSCALE_MCMD_YSIZE CBUS_REG_ADDR(PSCALE_MCMD_YSIZE)
#define P_PSCALE_RBUF_START_BLKX CBUS_REG_ADDR(PSCALE_RBUF_START_BLKX)
#define P_PSCALE_RBUF_START_BLKY CBUS_REG_ADDR(PSCALE_RBUF_START_BLKY)
#define P_PSCALE_PICO_SHIFT_XY CBUS_REG_ADDR(PSCALE_PICO_SHIFT_XY)
#define P_PSCALE_CTRL1 CBUS_REG_ADDR(PSCALE_CTRL1)
#define P_PSCALE_SRCKEY_CTRL0 CBUS_REG_ADDR(PSCALE_SRCKEY_CTRL0)
#define P_PSCALE_SRCKEY_CTRL1 CBUS_REG_ADDR(PSCALE_SRCKEY_CTRL1)
#define P_PSCALE_CANVAS_RD_ADDR CBUS_REG_ADDR(PSCALE_CANVAS_RD_ADDR)
#define P_PSCALE_CANVAS_WR_ADDR CBUS_REG_ADDR(PSCALE_CANVAS_WR_ADDR)
#define P_PSCALE_CTRL2 CBUS_REG_ADDR(PSCALE_CTRL2)
#define P_MC_MPORT_CTRL CBUS_REG_ADDR(MC_MPORT_CTRL)
#define P_MC_MPORT_DAT CBUS_REG_ADDR(MC_MPORT_DAT)
#define P_MC_WT_PRED_CTRL CBUS_REG_ADDR(MC_WT_PRED_CTRL)
#define P_MC_MBBOT_ST_EVEN_ADDR CBUS_REG_ADDR(MC_MBBOT_ST_EVEN_ADDR)
#define P_MC_MBBOT_ST_ODD_ADDR CBUS_REG_ADDR(MC_MBBOT_ST_ODD_ADDR)
#define P_MC_DPDN_MB_XY CBUS_REG_ADDR(MC_DPDN_MB_XY)
#define P_MC_OMDN_MB_XY CBUS_REG_ADDR(MC_OMDN_MB_XY)
#define P_MC_HCMDBUF_H CBUS_REG_ADDR(MC_HCMDBUF_H)
#define P_MC_HCMDBUF_L CBUS_REG_ADDR(MC_HCMDBUF_L)
#define P_MC_HCMD_H CBUS_REG_ADDR(MC_HCMD_H)
#define P_MC_HCMD_L CBUS_REG_ADDR(MC_HCMD_L)
#define P_MC_IDCT_DAT CBUS_REG_ADDR(MC_IDCT_DAT)
#define P_MC_CTRL_GCLK_CTRL CBUS_REG_ADDR(MC_CTRL_GCLK_CTRL)
#define P_MC_OTHER_GCLK_CTRL CBUS_REG_ADDR(MC_OTHER_GCLK_CTRL)
#define P_MC_CTRL2 CBUS_REG_ADDR(MC_CTRL2)
#define P_MDEC_PIC_DC_CTRL CBUS_REG_ADDR(MDEC_PIC_DC_CTRL)
#define P_MDEC_PIC_DC_STATUS CBUS_REG_ADDR(MDEC_PIC_DC_STATUS)
#define P_ANC0_CANVAS_ADDR CBUS_REG_ADDR(ANC0_CANVAS_ADDR)
#define P_ANC1_CANVAS_ADDR CBUS_REG_ADDR(ANC1_CANVAS_ADDR)
#define P_ANC2_CANVAS_ADDR CBUS_REG_ADDR(ANC2_CANVAS_ADDR)
#define P_ANC3_CANVAS_ADDR CBUS_REG_ADDR(ANC3_CANVAS_ADDR)
#define P_ANC4_CANVAS_ADDR CBUS_REG_ADDR(ANC4_CANVAS_ADDR)
#define P_ANC5_CANVAS_ADDR CBUS_REG_ADDR(ANC5_CANVAS_ADDR)
#define P_ANC6_CANVAS_ADDR CBUS_REG_ADDR(ANC6_CANVAS_ADDR)
#define P_ANC7_CANVAS_ADDR CBUS_REG_ADDR(ANC7_CANVAS_ADDR)
#define P_ANC8_CANVAS_ADDR CBUS_REG_ADDR(ANC8_CANVAS_ADDR)
#define P_ANC9_CANVAS_ADDR CBUS_REG_ADDR(ANC9_CANVAS_ADDR)
#define P_ANC10_CANVAS_ADDR CBUS_REG_ADDR(ANC10_CANVAS_ADDR)
#define P_ANC11_CANVAS_ADDR CBUS_REG_ADDR(ANC11_CANVAS_ADDR)
#define P_ANC12_CANVAS_ADDR CBUS_REG_ADDR(ANC12_CANVAS_ADDR)
#define P_ANC13_CANVAS_ADDR CBUS_REG_ADDR(ANC13_CANVAS_ADDR)
#define P_ANC14_CANVAS_ADDR CBUS_REG_ADDR(ANC14_CANVAS_ADDR)
#define P_ANC15_CANVAS_ADDR CBUS_REG_ADDR(ANC15_CANVAS_ADDR)
#define P_ANC16_CANVAS_ADDR CBUS_REG_ADDR(ANC16_CANVAS_ADDR)
#define P_ANC17_CANVAS_ADDR CBUS_REG_ADDR(ANC17_CANVAS_ADDR)
#define P_ANC18_CANVAS_ADDR CBUS_REG_ADDR(ANC18_CANVAS_ADDR)
#define P_ANC19_CANVAS_ADDR CBUS_REG_ADDR(ANC19_CANVAS_ADDR)
#define P_ANC20_CANVAS_ADDR CBUS_REG_ADDR(ANC20_CANVAS_ADDR)
#define P_ANC21_CANVAS_ADDR CBUS_REG_ADDR(ANC21_CANVAS_ADDR)
#define P_ANC22_CANVAS_ADDR CBUS_REG_ADDR(ANC22_CANVAS_ADDR)
#define P_ANC23_CANVAS_ADDR CBUS_REG_ADDR(ANC23_CANVAS_ADDR)
#define P_ANC24_CANVAS_ADDR CBUS_REG_ADDR(ANC24_CANVAS_ADDR)
#define P_ANC25_CANVAS_ADDR CBUS_REG_ADDR(ANC25_CANVAS_ADDR)
#define P_ANC26_CANVAS_ADDR CBUS_REG_ADDR(ANC26_CANVAS_ADDR)
#define P_ANC27_CANVAS_ADDR CBUS_REG_ADDR(ANC27_CANVAS_ADDR)
#define P_ANC28_CANVAS_ADDR CBUS_REG_ADDR(ANC28_CANVAS_ADDR)
#define P_ANC29_CANVAS_ADDR CBUS_REG_ADDR(ANC29_CANVAS_ADDR)
#define P_ANC30_CANVAS_ADDR CBUS_REG_ADDR(ANC30_CANVAS_ADDR)
#define P_ANC31_CANVAS_ADDR CBUS_REG_ADDR(ANC31_CANVAS_ADDR)
#define P_DBKR_CANVAS_ADDR CBUS_REG_ADDR(DBKR_CANVAS_ADDR)
#define P_DBKW_CANVAS_ADDR CBUS_REG_ADDR(DBKW_CANVAS_ADDR)
#define P_REC_CANVAS_ADDR CBUS_REG_ADDR(REC_CANVAS_ADDR)
#define P_CURR_CANVAS_CTRL CBUS_REG_ADDR(CURR_CANVAS_CTRL)
#define P_AV_SCRATCH_0 CBUS_REG_ADDR(AV_SCRATCH_0)
#define P_AV_SCRATCH_1 CBUS_REG_ADDR(AV_SCRATCH_1)
#define P_AV_SCRATCH_2 CBUS_REG_ADDR(AV_SCRATCH_2)
#define P_AV_SCRATCH_3 CBUS_REG_ADDR(AV_SCRATCH_3)
#define P_AV_SCRATCH_4 CBUS_REG_ADDR(AV_SCRATCH_4)
#define P_AV_SCRATCH_5 CBUS_REG_ADDR(AV_SCRATCH_5)
#define P_AV_SCRATCH_6 CBUS_REG_ADDR(AV_SCRATCH_6)
#define P_AV_SCRATCH_7 CBUS_REG_ADDR(AV_SCRATCH_7)
#define P_AV_SCRATCH_8 CBUS_REG_ADDR(AV_SCRATCH_8)
#define P_AV_SCRATCH_9 CBUS_REG_ADDR(AV_SCRATCH_9)
#define P_AV_SCRATCH_A CBUS_REG_ADDR(AV_SCRATCH_A)
#define P_AV_SCRATCH_B CBUS_REG_ADDR(AV_SCRATCH_B)
#define P_AV_SCRATCH_C CBUS_REG_ADDR(AV_SCRATCH_C)
#define P_AV_SCRATCH_D CBUS_REG_ADDR(AV_SCRATCH_D)
#define P_AV_SCRATCH_E CBUS_REG_ADDR(AV_SCRATCH_E)
#define P_AV_SCRATCH_F CBUS_REG_ADDR(AV_SCRATCH_F)
#define P_AV_SCRATCH_G CBUS_REG_ADDR(AV_SCRATCH_G)
#define P_AV_SCRATCH_H CBUS_REG_ADDR(AV_SCRATCH_H)
#define P_AV_SCRATCH_I CBUS_REG_ADDR(AV_SCRATCH_I)
#define P_AV_SCRATCH_J CBUS_REG_ADDR(AV_SCRATCH_J)
#define P_AV_SCRATCH_K CBUS_REG_ADDR(AV_SCRATCH_K)
#define P_AV_SCRATCH_L CBUS_REG_ADDR(AV_SCRATCH_L)
#define P_AV_SCRATCH_M CBUS_REG_ADDR(AV_SCRATCH_M)
#define P_AV_SCRATCH_N CBUS_REG_ADDR(AV_SCRATCH_N)
#define P_WRRSP_CO_MB CBUS_REG_ADDR(WRRSP_CO_MB)
#define P_WRRSP_DCAC CBUS_REG_ADDR(WRRSP_DCAC)
#define P_MC_ENABLE CBUS_REG_ADDR(MC_ENABLE)
#define P_SKIP_MB CBUS_REG_ADDR(SKIP_MB)
#define P_INTRA_MB CBUS_REG_ADDR(INTRA_MB)
#define P_BWD_PRED CBUS_REG_ADDR(BWD_PRED)
#define P_FWD_PRED CBUS_REG_ADDR(FWD_PRED)
#define P_FLD_MOT CBUS_REG_ADDR(FLD_MOT)
#define P_FRM_16x8_MOT CBUS_REG_ADDR(FRM_16x8_MOT)
#define P_DUAL_PRM_MOT CBUS_REG_ADDR(DUAL_PRM_MOT)
#define P_FRM_DCT CBUS_REG_ADDR(FRM_DCT)
#define P_FLD_DCT CBUS_REG_ADDR(FLD_DCT)
#define P_I_PIC CBUS_REG_ADDR(I_PIC)
#define P_P_PIC CBUS_REG_ADDR(P_PIC)
#define P_B_PIC CBUS_REG_ADDR(B_PIC)
#define P_FLD_PIC CBUS_REG_ADDR(FLD_PIC)
#define P_FRM_PIC CBUS_REG_ADDR(FRM_PIC)
#define P_DBLK_RST CBUS_REG_ADDR(DBLK_RST)
#define P_DBLK_CTRL CBUS_REG_ADDR(DBLK_CTRL)
#define P_DBLK_MB_WID_HEIGHT CBUS_REG_ADDR(DBLK_MB_WID_HEIGHT)
#define P_DBLK_STATUS CBUS_REG_ADDR(DBLK_STATUS)
#define P_DBLK_CMD_CTRL CBUS_REG_ADDR(DBLK_CMD_CTRL)
#define P_DBLK_MB_XY CBUS_REG_ADDR(DBLK_MB_XY)
#define P_DBLK_QP CBUS_REG_ADDR(DBLK_QP)
#define P_DBLK_Y_BHFILT CBUS_REG_ADDR(DBLK_Y_BHFILT)
#define P_DBLK_Y_BHFILT_HIGH CBUS_REG_ADDR(DBLK_Y_BHFILT_HIGH)
#define P_DBLK_Y_BVFILT CBUS_REG_ADDR(DBLK_Y_BVFILT)
#define P_DBLK_CB_BFILT CBUS_REG_ADDR(DBLK_CB_BFILT)
#define P_DBLK_CR_BFILT CBUS_REG_ADDR(DBLK_CR_BFILT)
#define P_DBLK_Y_HFILT CBUS_REG_ADDR(DBLK_Y_HFILT)
#define P_DBLK_Y_HFILT_HIGH CBUS_REG_ADDR(DBLK_Y_HFILT_HIGH)
#define P_DBLK_Y_VFILT CBUS_REG_ADDR(DBLK_Y_VFILT)
#define P_DBLK_CB_FILT CBUS_REG_ADDR(DBLK_CB_FILT)
#define P_DBLK_CR_FILT CBUS_REG_ADDR(DBLK_CR_FILT)
#define P_DBLK_BETAX_QP_SEL CBUS_REG_ADDR(DBLK_BETAX_QP_SEL)
#define P_DBLK_CLIP_CTRL0 CBUS_REG_ADDR(DBLK_CLIP_CTRL0)
#define P_DBLK_CLIP_CTRL1 CBUS_REG_ADDR(DBLK_CLIP_CTRL1)
#define P_DBLK_CLIP_CTRL2 CBUS_REG_ADDR(DBLK_CLIP_CTRL2)
#define P_DBLK_CLIP_CTRL3 CBUS_REG_ADDR(DBLK_CLIP_CTRL3)
#define P_DBLK_CLIP_CTRL4 CBUS_REG_ADDR(DBLK_CLIP_CTRL4)
#define P_DBLK_CLIP_CTRL5 CBUS_REG_ADDR(DBLK_CLIP_CTRL5)
#define P_DBLK_CLIP_CTRL6 CBUS_REG_ADDR(DBLK_CLIP_CTRL6)
#define P_DBLK_CLIP_CTRL7 CBUS_REG_ADDR(DBLK_CLIP_CTRL7)
#define P_DBLK_CLIP_CTRL8 CBUS_REG_ADDR(DBLK_CLIP_CTRL8)
#define P_DBLK_STATUS1 CBUS_REG_ADDR(DBLK_STATUS1)
#define P_DBLK_GCLK_FREE CBUS_REG_ADDR(DBLK_GCLK_FREE)
#define P_DBLK_GCLK_OFF CBUS_REG_ADDR(DBLK_GCLK_OFF)
#define P_DBLK_CBPY CBUS_REG_ADDR(DBLK_CBPY)
#define P_DBLK_CBPY_ADJ CBUS_REG_ADDR(DBLK_CBPY_ADJ)
#define P_DBLK_CBPC CBUS_REG_ADDR(DBLK_CBPC)
#define P_DBLK_CBPC_ADJ CBUS_REG_ADDR(DBLK_CBPC_ADJ)
#define P_DBLK_VHMVD CBUS_REG_ADDR(DBLK_VHMVD)
#define P_DBLK_STRONG CBUS_REG_ADDR(DBLK_STRONG)
#define P_DBLK_RV8_QUANT CBUS_REG_ADDR(DBLK_RV8_QUANT)
#define P_DBLK_CBUS_HCMD2 CBUS_REG_ADDR(DBLK_CBUS_HCMD2)
#define P_DBLK_CBUS_HCMD1 CBUS_REG_ADDR(DBLK_CBUS_HCMD1)
#define P_DBLK_CBUS_HCMD0 CBUS_REG_ADDR(DBLK_CBUS_HCMD0)
#define P_DBLK_VLD_HCMD2 CBUS_REG_ADDR(DBLK_VLD_HCMD2)
#define P_DBLK_VLD_HCMD1 CBUS_REG_ADDR(DBLK_VLD_HCMD1)
#define P_DBLK_VLD_HCMD0 CBUS_REG_ADDR(DBLK_VLD_HCMD0)
#define P_DBLK_OST_YBASE CBUS_REG_ADDR(DBLK_OST_YBASE)
#define P_DBLK_OST_CBCRDIFF CBUS_REG_ADDR(DBLK_OST_CBCRDIFF)
#define P_DBLK_CTRL1 CBUS_REG_ADDR(DBLK_CTRL1)
#define P_VIU_ADDR_START CBUS_REG_ADDR(VIU_ADDR_START)
#define P_VIU_ADDR_END CBUS_REG_ADDR(VIU_ADDR_END)
#define P_TRACE_REG CBUS_REG_ADDR(TRACE_REG)
#define P_VIU_OSD1_CTRL_STAT CBUS_REG_ADDR(VIU_OSD1_CTRL_STAT)
#define P_VIU_OSD1_CTRL_STAT2 CBUS_REG_ADDR(VIU_OSD1_CTRL_STAT2)
#define P_VIU_OSD1_COLOR_ADDR CBUS_REG_ADDR(VIU_OSD1_COLOR_ADDR)
#define P_VIU_OSD1_COLOR CBUS_REG_ADDR(VIU_OSD1_COLOR)
#define P_VIU_OSD1_TCOLOR_AG0 CBUS_REG_ADDR(VIU_OSD1_TCOLOR_AG0)
#define P_VIU_OSD1_TCOLOR_AG1 CBUS_REG_ADDR(VIU_OSD1_TCOLOR_AG1)
#define P_VIU_OSD1_TCOLOR_AG2 CBUS_REG_ADDR(VIU_OSD1_TCOLOR_AG2)
#define P_VIU_OSD1_TCOLOR_AG3 CBUS_REG_ADDR(VIU_OSD1_TCOLOR_AG3)
#define P_VIU_OSD1_BLK0_CFG_W0 CBUS_REG_ADDR(VIU_OSD1_BLK0_CFG_W0)
#define P_VIU_OSD1_BLK1_CFG_W0 CBUS_REG_ADDR(VIU_OSD1_BLK1_CFG_W0)
#define P_VIU_OSD1_BLK2_CFG_W0 CBUS_REG_ADDR(VIU_OSD1_BLK2_CFG_W0)
#define P_VIU_OSD1_BLK3_CFG_W0 CBUS_REG_ADDR(VIU_OSD1_BLK3_CFG_W0)
#define P_VIU_OSD1_BLK0_CFG_W1 CBUS_REG_ADDR(VIU_OSD1_BLK0_CFG_W1)
#define P_VIU_OSD1_BLK1_CFG_W1 CBUS_REG_ADDR(VIU_OSD1_BLK1_CFG_W1)
#define P_VIU_OSD1_BLK2_CFG_W1 CBUS_REG_ADDR(VIU_OSD1_BLK2_CFG_W1)
#define P_VIU_OSD1_BLK3_CFG_W1 CBUS_REG_ADDR(VIU_OSD1_BLK3_CFG_W1)
#define P_VIU_OSD1_BLK0_CFG_W2 CBUS_REG_ADDR(VIU_OSD1_BLK0_CFG_W2)
#define P_VIU_OSD1_BLK1_CFG_W2 CBUS_REG_ADDR(VIU_OSD1_BLK1_CFG_W2)
#define P_VIU_OSD1_BLK2_CFG_W2 CBUS_REG_ADDR(VIU_OSD1_BLK2_CFG_W2)
#define P_VIU_OSD1_BLK3_CFG_W2 CBUS_REG_ADDR(VIU_OSD1_BLK3_CFG_W2)
#define P_VIU_OSD1_BLK0_CFG_W3 CBUS_REG_ADDR(VIU_OSD1_BLK0_CFG_W3)
#define P_VIU_OSD1_BLK1_CFG_W3 CBUS_REG_ADDR(VIU_OSD1_BLK1_CFG_W3)
#define P_VIU_OSD1_BLK2_CFG_W3 CBUS_REG_ADDR(VIU_OSD1_BLK2_CFG_W3)
#define P_VIU_OSD1_BLK3_CFG_W3 CBUS_REG_ADDR(VIU_OSD1_BLK3_CFG_W3)
#define P_VIU_OSD1_BLK0_CFG_W4 CBUS_REG_ADDR(VIU_OSD1_BLK0_CFG_W4)
#define P_VIU_OSD1_BLK1_CFG_W4 CBUS_REG_ADDR(VIU_OSD1_BLK1_CFG_W4)
#define P_VIU_OSD1_BLK2_CFG_W4 CBUS_REG_ADDR(VIU_OSD1_BLK2_CFG_W4)
#define P_VIU_OSD1_BLK3_CFG_W4 CBUS_REG_ADDR(VIU_OSD1_BLK3_CFG_W4)
#define P_VIU_OSD1_FIFO_CTRL_STAT CBUS_REG_ADDR(VIU_OSD1_FIFO_CTRL_STAT)
#define P_VIU_OSD1_TEST_RDDATA CBUS_REG_ADDR(VIU_OSD1_TEST_RDDATA)
#define P_VIU_OSD2_CTRL_STAT CBUS_REG_ADDR(VIU_OSD2_CTRL_STAT)
#define P_VIU_OSD2_CTRL_STAT2 CBUS_REG_ADDR(VIU_OSD2_CTRL_STAT2)
#define P_VIU_OSD2_COLOR_ADDR CBUS_REG_ADDR(VIU_OSD2_COLOR_ADDR)
#define P_VIU_OSD2_COLOR CBUS_REG_ADDR(VIU_OSD2_COLOR)
#define P_VIU_OSD2_HL1_H_START_END CBUS_REG_ADDR(VIU_OSD2_HL1_H_START_END)
#define P_VIU_OSD2_HL1_V_START_END CBUS_REG_ADDR(VIU_OSD2_HL1_V_START_END)
#define P_VIU_OSD2_HL2_H_START_END CBUS_REG_ADDR(VIU_OSD2_HL2_H_START_END)
#define P_VIU_OSD2_HL2_V_START_END CBUS_REG_ADDR(VIU_OSD2_HL2_V_START_END)
#define P_VIU_OSD2_TCOLOR_AG0 CBUS_REG_ADDR(VIU_OSD2_TCOLOR_AG0)
#define P_VIU_OSD2_TCOLOR_AG1 CBUS_REG_ADDR(VIU_OSD2_TCOLOR_AG1)
#define P_VIU_OSD2_TCOLOR_AG2 CBUS_REG_ADDR(VIU_OSD2_TCOLOR_AG2)
#define P_VIU_OSD2_TCOLOR_AG3 CBUS_REG_ADDR(VIU_OSD2_TCOLOR_AG3)
#define P_VIU_OSD2_BLK0_CFG_W0 CBUS_REG_ADDR(VIU_OSD2_BLK0_CFG_W0)
#define P_VIU_OSD2_BLK1_CFG_W0 CBUS_REG_ADDR(VIU_OSD2_BLK1_CFG_W0)
#define P_VIU_OSD2_BLK2_CFG_W0 CBUS_REG_ADDR(VIU_OSD2_BLK2_CFG_W0)
#define P_VIU_OSD2_BLK3_CFG_W0 CBUS_REG_ADDR(VIU_OSD2_BLK3_CFG_W0)
#define P_VIU_OSD2_BLK0_CFG_W1 CBUS_REG_ADDR(VIU_OSD2_BLK0_CFG_W1)
#define P_VIU_OSD2_BLK1_CFG_W1 CBUS_REG_ADDR(VIU_OSD2_BLK1_CFG_W1)
#define P_VIU_OSD2_BLK2_CFG_W1 CBUS_REG_ADDR(VIU_OSD2_BLK2_CFG_W1)
#define P_VIU_OSD2_BLK3_CFG_W1 CBUS_REG_ADDR(VIU_OSD2_BLK3_CFG_W1)
#define P_VIU_OSD2_BLK0_CFG_W2 CBUS_REG_ADDR(VIU_OSD2_BLK0_CFG_W2)
#define P_VIU_OSD2_BLK1_CFG_W2 CBUS_REG_ADDR(VIU_OSD2_BLK1_CFG_W2)
#define P_VIU_OSD2_BLK2_CFG_W2 CBUS_REG_ADDR(VIU_OSD2_BLK2_CFG_W2)
#define P_VIU_OSD2_BLK3_CFG_W2 CBUS_REG_ADDR(VIU_OSD2_BLK3_CFG_W2)
#define P_VIU_OSD2_BLK0_CFG_W3 CBUS_REG_ADDR(VIU_OSD2_BLK0_CFG_W3)
#define P_VIU_OSD2_BLK1_CFG_W3 CBUS_REG_ADDR(VIU_OSD2_BLK1_CFG_W3)
#define P_VIU_OSD2_BLK2_CFG_W3 CBUS_REG_ADDR(VIU_OSD2_BLK2_CFG_W3)
#define P_VIU_OSD2_BLK3_CFG_W3 CBUS_REG_ADDR(VIU_OSD2_BLK3_CFG_W3)
#define P_VIU_OSD2_BLK0_CFG_W4 CBUS_REG_ADDR(VIU_OSD2_BLK0_CFG_W4)
#define P_VIU_OSD2_BLK1_CFG_W4 CBUS_REG_ADDR(VIU_OSD2_BLK1_CFG_W4)
#define P_VIU_OSD2_BLK2_CFG_W4 CBUS_REG_ADDR(VIU_OSD2_BLK2_CFG_W4)
#define P_VIU_OSD2_BLK3_CFG_W4 CBUS_REG_ADDR(VIU_OSD2_BLK3_CFG_W4)
#define P_VIU_OSD2_FIFO_CTRL_STAT CBUS_REG_ADDR(VIU_OSD2_FIFO_CTRL_STAT)
#define P_VIU_OSD2_TEST_RDDATA CBUS_REG_ADDR(VIU_OSD2_TEST_RDDATA)
#define P_VD1_IF0_GEN_REG CBUS_REG_ADDR(VD1_IF0_GEN_REG)
#define P_VD1_IF0_CANVAS0 CBUS_REG_ADDR(VD1_IF0_CANVAS0)
#define P_VD1_IF0_CANVAS1 CBUS_REG_ADDR(VD1_IF0_CANVAS1)
#define P_VD1_IF0_LUMA_X0 CBUS_REG_ADDR(VD1_IF0_LUMA_X0)
#define P_VD1_IF0_LUMA_Y0 CBUS_REG_ADDR(VD1_IF0_LUMA_Y0)
#define P_VD1_IF0_CHROMA_X0 CBUS_REG_ADDR(VD1_IF0_CHROMA_X0)
#define P_VD1_IF0_CHROMA_Y0 CBUS_REG_ADDR(VD1_IF0_CHROMA_Y0)
#define P_VD1_IF0_LUMA_X1 CBUS_REG_ADDR(VD1_IF0_LUMA_X1)
#define P_VD1_IF0_LUMA_Y1 CBUS_REG_ADDR(VD1_IF0_LUMA_Y1)
#define P_VD1_IF0_CHROMA_X1 CBUS_REG_ADDR(VD1_IF0_CHROMA_X1)
#define P_VD1_IF0_CHROMA_Y1 CBUS_REG_ADDR(VD1_IF0_CHROMA_Y1)
#define P_VD1_IF0_RPT_LOOP CBUS_REG_ADDR(VD1_IF0_RPT_LOOP)
#define P_VD1_IF0_LUMA0_RPT_PAT CBUS_REG_ADDR(VD1_IF0_LUMA0_RPT_PAT)
#define P_VD1_IF0_CHROMA0_RPT_PAT CBUS_REG_ADDR(VD1_IF0_CHROMA0_RPT_PAT)
#define P_VD1_IF0_LUMA1_RPT_PAT CBUS_REG_ADDR(VD1_IF0_LUMA1_RPT_PAT)
#define P_VD1_IF0_CHROMA1_RPT_PAT CBUS_REG_ADDR(VD1_IF0_CHROMA1_RPT_PAT)
#define P_VD1_IF0_LUMA_PSEL CBUS_REG_ADDR(VD1_IF0_LUMA_PSEL)
#define P_VD1_IF0_CHROMA_PSEL CBUS_REG_ADDR(VD1_IF0_CHROMA_PSEL)
#define P_VD1_IF0_DUMMY_PIXEL CBUS_REG_ADDR(VD1_IF0_DUMMY_PIXEL)
#define P_VD1_IF0_LUMA_FIFO_SIZE CBUS_REG_ADDR(VD1_IF0_LUMA_FIFO_SIZE)
#define P_VD1_IF0_RANGE_MAP_Y CBUS_REG_ADDR(VD1_IF0_RANGE_MAP_Y)
#define P_VD1_IF0_RANGE_MAP_CB CBUS_REG_ADDR(VD1_IF0_RANGE_MAP_CB)
#define P_VD1_IF0_RANGE_MAP_CR CBUS_REG_ADDR(VD1_IF0_RANGE_MAP_CR)
#define P_VIU_VD1_FMT_CTRL CBUS_REG_ADDR(VIU_VD1_FMT_CTRL)
#define P_VIU_VD1_FMT_W CBUS_REG_ADDR(VIU_VD1_FMT_W)
#define P_VD2_IF0_GEN_REG CBUS_REG_ADDR(VD2_IF0_GEN_REG)
#define P_VD2_IF0_CANVAS0 CBUS_REG_ADDR(VD2_IF0_CANVAS0)
#define P_VD2_IF0_CANVAS1 CBUS_REG_ADDR(VD2_IF0_CANVAS1)
#define P_VD2_IF0_LUMA_X0 CBUS_REG_ADDR(VD2_IF0_LUMA_X0)
#define P_VD2_IF0_LUMA_Y0 CBUS_REG_ADDR(VD2_IF0_LUMA_Y0)
#define P_VD2_IF0_CHROMA_X0 CBUS_REG_ADDR(VD2_IF0_CHROMA_X0)
#define P_VD2_IF0_CHROMA_Y0 CBUS_REG_ADDR(VD2_IF0_CHROMA_Y0)
#define P_VD2_IF0_LUMA_X1 CBUS_REG_ADDR(VD2_IF0_LUMA_X1)
#define P_VD2_IF0_LUMA_Y1 CBUS_REG_ADDR(VD2_IF0_LUMA_Y1)
#define P_VD2_IF0_CHROMA_X1 CBUS_REG_ADDR(VD2_IF0_CHROMA_X1)
#define P_VD2_IF0_CHROMA_Y1 CBUS_REG_ADDR(VD2_IF0_CHROMA_Y1)
#define P_VD2_IF0_RPT_LOOP CBUS_REG_ADDR(VD2_IF0_RPT_LOOP)
#define P_VD2_IF0_LUMA0_RPT_PAT CBUS_REG_ADDR(VD2_IF0_LUMA0_RPT_PAT)
#define P_VD2_IF0_CHROMA0_RPT_PAT CBUS_REG_ADDR(VD2_IF0_CHROMA0_RPT_PAT)
#define P_VD2_IF0_LUMA1_RPT_PAT CBUS_REG_ADDR(VD2_IF0_LUMA1_RPT_PAT)
#define P_VD2_IF0_CHROMA1_RPT_PAT CBUS_REG_ADDR(VD2_IF0_CHROMA1_RPT_PAT)
#define P_VD2_IF0_LUMA_PSEL CBUS_REG_ADDR(VD2_IF0_LUMA_PSEL)
#define P_VD2_IF0_CHROMA_PSEL CBUS_REG_ADDR(VD2_IF0_CHROMA_PSEL)
#define P_VD2_IF0_DUMMY_PIXEL CBUS_REG_ADDR(VD2_IF0_DUMMY_PIXEL)
#define P_VD2_IF0_LUMA_FIFO_SIZE CBUS_REG_ADDR(VD2_IF0_LUMA_FIFO_SIZE)
#define P_VD2_IF0_RANGE_MAP_Y CBUS_REG_ADDR(VD2_IF0_RANGE_MAP_Y)
#define P_VD2_IF0_RANGE_MAP_CB CBUS_REG_ADDR(VD2_IF0_RANGE_MAP_CB)
#define P_VD2_IF0_RANGE_MAP_CR CBUS_REG_ADDR(VD2_IF0_RANGE_MAP_CR)
#define P_VIU_VD2_FMT_CTRL CBUS_REG_ADDR(VIU_VD2_FMT_CTRL)
#define P_VIU_VD2_FMT_W CBUS_REG_ADDR(VIU_VD2_FMT_W)
#define P_DI_PRE_CTRL CBUS_REG_ADDR(DI_PRE_CTRL)
#define P_DI_POST_CTRL CBUS_REG_ADDR(DI_POST_CTRL)
#define P_DI_POST_SIZE CBUS_REG_ADDR(DI_POST_SIZE)
#define P_DI_PRE_SIZE CBUS_REG_ADDR(DI_PRE_SIZE)
#define P_DI_EI_CTRL0 CBUS_REG_ADDR(DI_EI_CTRL0)
#define P_DI_EI_CTRL1 CBUS_REG_ADDR(DI_EI_CTRL1)
#define P_DI_EI_CTRL2 CBUS_REG_ADDR(DI_EI_CTRL2)
#define P_DI_NRMTN_CTRL0 CBUS_REG_ADDR(DI_NRMTN_CTRL0)
#define P_DI_NR_CTRL1 CBUS_REG_ADDR(DI_NR_CTRL1)
#define P_DI_BLEND_CTRL CBUS_REG_ADDR(DI_BLEND_CTRL)
#define P_DI_BLEND_REG0_X CBUS_REG_ADDR(DI_BLEND_REG0_X)
#define P_DI_BLEND_REG0_Y CBUS_REG_ADDR(DI_BLEND_REG0_Y)
#define P_DI_BLEND_REG1_X CBUS_REG_ADDR(DI_BLEND_REG1_X)
#define P_DI_BLEND_REG1_Y CBUS_REG_ADDR(DI_BLEND_REG1_Y)
#define P_DI_BLEND_REG2_X CBUS_REG_ADDR(DI_BLEND_REG2_X)
#define P_DI_BLEND_REG2_Y CBUS_REG_ADDR(DI_BLEND_REG2_Y)
#define P_DI_BLEND_REG3_X CBUS_REG_ADDR(DI_BLEND_REG3_X)
#define P_DI_BLEND_REG3_Y CBUS_REG_ADDR(DI_BLEND_REG3_Y)
#define P_DI_MC_REG0_X CBUS_REG_ADDR(DI_MC_REG0_X)
#define P_DI_MC_REG0_Y CBUS_REG_ADDR(DI_MC_REG0_Y)
#define P_DI_MC_REG1_X CBUS_REG_ADDR(DI_MC_REG1_X)
#define P_DI_MC_REG1_Y CBUS_REG_ADDR(DI_MC_REG1_Y)
#define P_DI_MC_REG2_X CBUS_REG_ADDR(DI_MC_REG2_X)
#define P_DI_MC_REG2_Y CBUS_REG_ADDR(DI_MC_REG2_Y)
#define P_DI_MC_REG3_X CBUS_REG_ADDR(DI_MC_REG3_X)
#define P_DI_MC_REG3_Y CBUS_REG_ADDR(DI_MC_REG3_Y)
#define P_DI_MC_REG4_X CBUS_REG_ADDR(DI_MC_REG4_X)
#define P_DI_MC_REG4_Y CBUS_REG_ADDR(DI_MC_REG4_Y)
#define P_DI_MC_32LVL0 CBUS_REG_ADDR(DI_MC_32LVL0)
#define P_DI_MC_32LVL1 CBUS_REG_ADDR(DI_MC_32LVL1)
#define P_DI_MC_22LVL0 CBUS_REG_ADDR(DI_MC_22LVL0)
#define P_DI_MC_22LVL1 CBUS_REG_ADDR(DI_MC_22LVL1)
#define P_DI_MC_22LVL2 CBUS_REG_ADDR(DI_MC_22LVL2)
#define P_DI_MC_CTRL CBUS_REG_ADDR(DI_MC_CTRL)
#define P_DI_INTR_CTRL CBUS_REG_ADDR(DI_INTR_CTRL)
#define P_DI_INFO_ADDR CBUS_REG_ADDR(DI_INFO_ADDR)
#define P_DI_INFO_DATA CBUS_REG_ADDR(DI_INFO_DATA)
#define P_DI_PRE_HOLD CBUS_REG_ADDR(DI_PRE_HOLD)
#define P_DI_NRWR_X CBUS_REG_ADDR(DI_NRWR_X)
#define P_DI_NRWR_Y CBUS_REG_ADDR(DI_NRWR_Y)
#define P_DI_NRWR_CTRL CBUS_REG_ADDR(DI_NRWR_CTRL)
#define P_DI_MTNWR_X CBUS_REG_ADDR(DI_MTNWR_X)
#define P_DI_MTNWR_Y CBUS_REG_ADDR(DI_MTNWR_Y)
#define P_DI_MTNWR_CTRL CBUS_REG_ADDR(DI_MTNWR_CTRL)
#define P_DI_DIWR_X CBUS_REG_ADDR(DI_DIWR_X)
#define P_DI_DIWR_Y CBUS_REG_ADDR(DI_DIWR_Y)
#define P_DI_DIWR_CTRL CBUS_REG_ADDR(DI_DIWR_CTRL)
#define P_DI_MTNCRD_X CBUS_REG_ADDR(DI_MTNCRD_X)
#define P_DI_MTNCRD_Y CBUS_REG_ADDR(DI_MTNCRD_Y)
#define P_DI_MTNPRD_X CBUS_REG_ADDR(DI_MTNPRD_X)
#define P_DI_MTNPRD_Y CBUS_REG_ADDR(DI_MTNPRD_Y)
#define P_DI_MTNRD_CTRL CBUS_REG_ADDR(DI_MTNRD_CTRL)
#define P_DI_INP_GEN_REG CBUS_REG_ADDR(DI_INP_GEN_REG)
#define P_DI_INP_CANVAS0 CBUS_REG_ADDR(DI_INP_CANVAS0)
#define P_DI_INP_LUMA_X0 CBUS_REG_ADDR(DI_INP_LUMA_X0)
#define P_DI_INP_LUMA_Y0 CBUS_REG_ADDR(DI_INP_LUMA_Y0)
#define P_DI_INP_CHROMA_X0 CBUS_REG_ADDR(DI_INP_CHROMA_X0)
#define P_DI_INP_CHROMA_Y0 CBUS_REG_ADDR(DI_INP_CHROMA_Y0)
#define P_DI_INP_RPT_LOOP CBUS_REG_ADDR(DI_INP_RPT_LOOP)
#define P_DI_INP_LUMA0_RPT_PAT CBUS_REG_ADDR(DI_INP_LUMA0_RPT_PAT)
#define P_DI_INP_CHROMA0_RPT_PAT CBUS_REG_ADDR(DI_INP_CHROMA0_RPT_PAT)
#define P_DI_INP_DUMMY_PIXEL CBUS_REG_ADDR(DI_INP_DUMMY_PIXEL)
#define P_DI_INP_LUMA_FIFO_SIZE CBUS_REG_ADDR(DI_INP_LUMA_FIFO_SIZE)
#define P_DI_INP_RANGE_MAP_Y CBUS_REG_ADDR(DI_INP_RANGE_MAP_Y)
#define P_DI_INP_RANGE_MAP_CB CBUS_REG_ADDR(DI_INP_RANGE_MAP_CB)
#define P_DI_INP_RANGE_MAP_CR CBUS_REG_ADDR(DI_INP_RANGE_MAP_CR)
#define P_DI_INP_FMT_CTRL CBUS_REG_ADDR(DI_INP_FMT_CTRL)
#define P_DI_INP_FMT_W CBUS_REG_ADDR(DI_INP_FMT_W)
#define P_DI_MEM_GEN_REG CBUS_REG_ADDR(DI_MEM_GEN_REG)
#define P_DI_MEM_CANVAS0 CBUS_REG_ADDR(DI_MEM_CANVAS0)
#define P_DI_MEM_LUMA_X0 CBUS_REG_ADDR(DI_MEM_LUMA_X0)
#define P_DI_MEM_LUMA_Y0 CBUS_REG_ADDR(DI_MEM_LUMA_Y0)
#define P_DI_MEM_CHROMA_X0 CBUS_REG_ADDR(DI_MEM_CHROMA_X0)
#define P_DI_MEM_CHROMA_Y0 CBUS_REG_ADDR(DI_MEM_CHROMA_Y0)
#define P_DI_MEM_RPT_LOOP CBUS_REG_ADDR(DI_MEM_RPT_LOOP)
#define P_DI_MEM_LUMA0_RPT_PAT CBUS_REG_ADDR(DI_MEM_LUMA0_RPT_PAT)
#define P_DI_MEM_CHROMA0_RPT_PAT CBUS_REG_ADDR(DI_MEM_CHROMA0_RPT_PAT)
#define P_DI_MEM_DUMMY_PIXEL CBUS_REG_ADDR(DI_MEM_DUMMY_PIXEL)
#define P_DI_MEM_LUMA_FIFO_SIZE CBUS_REG_ADDR(DI_MEM_LUMA_FIFO_SIZE)
#define P_DI_MEM_RANGE_MAP_Y CBUS_REG_ADDR(DI_MEM_RANGE_MAP_Y)
#define P_DI_MEM_RANGE_MAP_CB CBUS_REG_ADDR(DI_MEM_RANGE_MAP_CB)
#define P_DI_MEM_RANGE_MAP_CR CBUS_REG_ADDR(DI_MEM_RANGE_MAP_CR)
#define P_DI_MEM_FMT_CTRL CBUS_REG_ADDR(DI_MEM_FMT_CTRL)
#define P_DI_MEM_FMT_W CBUS_REG_ADDR(DI_MEM_FMT_W)
#define P_DI_IF1_GEN_REG CBUS_REG_ADDR(DI_IF1_GEN_REG)
#define P_DI_IF1_CANVAS0 CBUS_REG_ADDR(DI_IF1_CANVAS0)
#define P_DI_IF1_LUMA_X0 CBUS_REG_ADDR(DI_IF1_LUMA_X0)
#define P_DI_IF1_LUMA_Y0 CBUS_REG_ADDR(DI_IF1_LUMA_Y0)
#define P_DI_IF1_CHROMA_X0 CBUS_REG_ADDR(DI_IF1_CHROMA_X0)
#define P_DI_IF1_CHROMA_Y0 CBUS_REG_ADDR(DI_IF1_CHROMA_Y0)
#define P_DI_IF1_RPT_LOOP CBUS_REG_ADDR(DI_IF1_RPT_LOOP)
#define P_DI_IF1_LUMA0_RPT_PAT CBUS_REG_ADDR(DI_IF1_LUMA0_RPT_PAT)
#define P_DI_IF1_CHROMA0_RPT_PAT CBUS_REG_ADDR(DI_IF1_CHROMA0_RPT_PAT)
#define P_DI_IF1_DUMMY_PIXEL CBUS_REG_ADDR(DI_IF1_DUMMY_PIXEL)
#define P_DI_IF1_LUMA_FIFO_SIZE CBUS_REG_ADDR(DI_IF1_LUMA_FIFO_SIZE)
#define P_DI_IF1_RANGE_MAP_Y CBUS_REG_ADDR(DI_IF1_RANGE_MAP_Y)
#define P_DI_IF1_RANGE_MAP_CB CBUS_REG_ADDR(DI_IF1_RANGE_MAP_CB)
#define P_DI_IF1_RANGE_MAP_CR CBUS_REG_ADDR(DI_IF1_RANGE_MAP_CR)
#define P_DI_IF1_FMT_CTRL CBUS_REG_ADDR(DI_IF1_FMT_CTRL)
#define P_DI_IF1_FMT_W CBUS_REG_ADDR(DI_IF1_FMT_W)
#define P_DI_CHAN2_GEN_REG CBUS_REG_ADDR(DI_CHAN2_GEN_REG)
#define P_DI_CHAN2_CANVAS CBUS_REG_ADDR(DI_CHAN2_CANVAS)
#define P_DI_CHAN2_LUMA_X CBUS_REG_ADDR(DI_CHAN2_LUMA_X)
#define P_DI_CHAN2_LUMA_Y CBUS_REG_ADDR(DI_CHAN2_LUMA_Y)
#define P_DI_CHAN2_RPT_LOOP CBUS_REG_ADDR(DI_CHAN2_RPT_LOOP)
#define P_DI_CHAN2_LUMA_RPT_PAT CBUS_REG_ADDR(DI_CHAN2_LUMA_RPT_PAT)
#define P_DI_CHAN2_DUMMY_PIXEL CBUS_REG_ADDR(DI_CHAN2_DUMMY_PIXEL)
#define P_DI_CHAN2_RANGE_MAP_Y CBUS_REG_ADDR(DI_CHAN2_RANGE_MAP_Y)
#define P_VFIFO2VD_CTL CBUS_REG_ADDR(VFIFO2VD_CTL)
#define P_VFIFO2VD_PIXEL_START CBUS_REG_ADDR(VFIFO2VD_PIXEL_START)
#define P_VFIFO2VD_PIXEL_END CBUS_REG_ADDR(VFIFO2VD_PIXEL_END)
#define P_VFIFO2VD_LINE_TOP_START CBUS_REG_ADDR(VFIFO2VD_LINE_TOP_START)
#define P_VFIFO2VD_LINE_TOP_END CBUS_REG_ADDR(VFIFO2VD_LINE_TOP_END)
#define P_VFIFO2VD_LINE_BOT_START CBUS_REG_ADDR(VFIFO2VD_LINE_BOT_START)
#define P_VFIFO2VD_LINE_BOT_END CBUS_REG_ADDR(VFIFO2VD_LINE_BOT_END)
#define P_VENC_SYNC_ROUTE CBUS_REG_ADDR(VENC_SYNC_ROUTE)
#define P_VENC_VIDEO_EXSRC CBUS_REG_ADDR(VENC_VIDEO_EXSRC)
#define P_VENC_DVI_SETTING CBUS_REG_ADDR(VENC_DVI_SETTING)
#define P_VENC_C656_CTRL CBUS_REG_ADDR(VENC_C656_CTRL)
#define P_VENC_UPSAMPLE_CTRL0 CBUS_REG_ADDR(VENC_UPSAMPLE_CTRL0)
#define P_VENC_UPSAMPLE_CTRL1 CBUS_REG_ADDR(VENC_UPSAMPLE_CTRL1)
#define P_VENC_UPSAMPLE_CTRL2 CBUS_REG_ADDR(VENC_UPSAMPLE_CTRL2)
#define P_TCON_INVERT_CTL CBUS_REG_ADDR(TCON_INVERT_CTL)
#define P_VENC_VIDEO_PROG_MODE CBUS_REG_ADDR(VENC_VIDEO_PROG_MODE)
#define P_VENC_ENCI_LINE CBUS_REG_ADDR(VENC_ENCI_LINE)
#define P_VENC_ENCI_PIXEL CBUS_REG_ADDR(VENC_ENCI_PIXEL)
#define P_VENC_ENCP_LINE CBUS_REG_ADDR(VENC_ENCP_LINE)
#define P_VENC_ENCP_PIXEL CBUS_REG_ADDR(VENC_ENCP_PIXEL)
#define P_VENC_STATA CBUS_REG_ADDR(VENC_STATA)
#define P_VENC_INTCTRL CBUS_REG_ADDR(VENC_INTCTRL)
#define P_VENC_INTFLAG CBUS_REG_ADDR(VENC_INTFLAG)
#define P_VENC_VIDEO_TST_EN CBUS_REG_ADDR(VENC_VIDEO_TST_EN)
#define P_VENC_VIDEO_TST_MDSEL CBUS_REG_ADDR(VENC_VIDEO_TST_MDSEL)
#define P_VENC_VIDEO_TST_Y CBUS_REG_ADDR(VENC_VIDEO_TST_Y)
#define P_VENC_VIDEO_TST_CB CBUS_REG_ADDR(VENC_VIDEO_TST_CB)
#define P_VENC_VIDEO_TST_CR CBUS_REG_ADDR(VENC_VIDEO_TST_CR)
#define P_VENC_VIDEO_TST_CLRBAR_STRT CBUS_REG_ADDR(VENC_VIDEO_TST_CLRBAR_STRT)
#define P_VENC_VIDEO_TST_CLRBAR_WIDTH CBUS_REG_ADDR(VENC_VIDEO_TST_CLRBAR_WIDTH)
#define P_VENC_VIDEO_TST_VDCNT_STSET CBUS_REG_ADDR(VENC_VIDEO_TST_VDCNT_STSET)
#define P_VENC_VDAC_DACSEL0 CBUS_REG_ADDR(VENC_VDAC_DACSEL0)
#define P_VENC_VDAC_DACSEL1 CBUS_REG_ADDR(VENC_VDAC_DACSEL1)
#define P_VENC_VDAC_DACSEL2 CBUS_REG_ADDR(VENC_VDAC_DACSEL2)
#define P_VENC_VDAC_DACSEL3 CBUS_REG_ADDR(VENC_VDAC_DACSEL3)
#define P_VENC_VDAC_DACSEL4 CBUS_REG_ADDR(VENC_VDAC_DACSEL4)
#define P_VENC_VDAC_DACSEL5 CBUS_REG_ADDR(VENC_VDAC_DACSEL5)
#define P_VENC_VDAC_SETTING CBUS_REG_ADDR(VENC_VDAC_SETTING)
#define P_VENC_VDAC_TST_VAL CBUS_REG_ADDR(VENC_VDAC_TST_VAL)
#define P_VENC_VDAC_DAC0_GAINCTRL CBUS_REG_ADDR(VENC_VDAC_DAC0_GAINCTRL)
#define P_VENC_VDAC_DAC0_OFFSET CBUS_REG_ADDR(VENC_VDAC_DAC0_OFFSET)
#define P_VENC_VDAC_DAC1_GAINCTRL CBUS_REG_ADDR(VENC_VDAC_DAC1_GAINCTRL)
#define P_VENC_VDAC_DAC1_OFFSET CBUS_REG_ADDR(VENC_VDAC_DAC1_OFFSET)
#define P_VENC_VDAC_DAC2_GAINCTRL CBUS_REG_ADDR(VENC_VDAC_DAC2_GAINCTRL)
#define P_VENC_VDAC_DAC2_OFFSET CBUS_REG_ADDR(VENC_VDAC_DAC2_OFFSET)
#define P_VENC_VDAC_DAC3_GAINCTRL CBUS_REG_ADDR(VENC_VDAC_DAC3_GAINCTRL)
#define P_VENC_VDAC_DAC3_OFFSET CBUS_REG_ADDR(VENC_VDAC_DAC3_OFFSET)
#define P_ENCP_VIDEO_EN CBUS_REG_ADDR(ENCP_VIDEO_EN)
#define P_ENCP_VIDEO_SYNC_MODE CBUS_REG_ADDR(ENCP_VIDEO_SYNC_MODE)
#define P_ENCP_MACV_EN CBUS_REG_ADDR(ENCP_MACV_EN)
#define P_ENCP_VIDEO_Y_SCL CBUS_REG_ADDR(ENCP_VIDEO_Y_SCL)
#define P_ENCP_VIDEO_PB_SCL CBUS_REG_ADDR(ENCP_VIDEO_PB_SCL)
#define P_ENCP_VIDEO_PR_SCL CBUS_REG_ADDR(ENCP_VIDEO_PR_SCL)
#define P_ENCP_VIDEO_SYNC_SCL CBUS_REG_ADDR(ENCP_VIDEO_SYNC_SCL)
#define P_ENCP_VIDEO_MACV_SCL CBUS_REG_ADDR(ENCP_VIDEO_MACV_SCL)
#define P_ENCP_VIDEO_Y_OFFST CBUS_REG_ADDR(ENCP_VIDEO_Y_OFFST)
#define P_ENCP_VIDEO_PB_OFFST CBUS_REG_ADDR(ENCP_VIDEO_PB_OFFST)
#define P_ENCP_VIDEO_PR_OFFST CBUS_REG_ADDR(ENCP_VIDEO_PR_OFFST)
#define P_ENCP_VIDEO_SYNC_OFFST CBUS_REG_ADDR(ENCP_VIDEO_SYNC_OFFST)
#define P_ENCP_VIDEO_MACV_OFFST CBUS_REG_ADDR(ENCP_VIDEO_MACV_OFFST)
#define P_ENCP_VIDEO_MODE CBUS_REG_ADDR(ENCP_VIDEO_MODE)
#define P_ENCP_VIDEO_MODE_ADV CBUS_REG_ADDR(ENCP_VIDEO_MODE_ADV)
#define P_ENCP_DBG_PX_RST CBUS_REG_ADDR(ENCP_DBG_PX_RST)
#define P_ENCP_DBG_LN_RST CBUS_REG_ADDR(ENCP_DBG_LN_RST)
#define P_ENCP_DBG_PX_INT CBUS_REG_ADDR(ENCP_DBG_PX_INT)
#define P_ENCP_DBG_LN_INT CBUS_REG_ADDR(ENCP_DBG_LN_INT)
#define P_ENCP_VIDEO_YFP1_HTIME CBUS_REG_ADDR(ENCP_VIDEO_YFP1_HTIME)
#define P_ENCP_VIDEO_YFP2_HTIME CBUS_REG_ADDR(ENCP_VIDEO_YFP2_HTIME)
#define P_ENCP_VIDEO_YC_DLY CBUS_REG_ADDR(ENCP_VIDEO_YC_DLY)
#define P_ENCP_VIDEO_MAX_PXCNT CBUS_REG_ADDR(ENCP_VIDEO_MAX_PXCNT)
#define P_ENCP_VIDEO_HSPULS_BEGIN CBUS_REG_ADDR(ENCP_VIDEO_HSPULS_BEGIN)
#define P_ENCP_VIDEO_HSPULS_END CBUS_REG_ADDR(ENCP_VIDEO_HSPULS_END)
#define P_ENCP_VIDEO_HSPULS_SWITCH CBUS_REG_ADDR(ENCP_VIDEO_HSPULS_SWITCH)
#define P_ENCP_VIDEO_VSPULS_BEGIN CBUS_REG_ADDR(ENCP_VIDEO_VSPULS_BEGIN)
#define P_ENCP_VIDEO_VSPULS_END CBUS_REG_ADDR(ENCP_VIDEO_VSPULS_END)
#define P_ENCP_VIDEO_VSPULS_BLINE CBUS_REG_ADDR(ENCP_VIDEO_VSPULS_BLINE)
#define P_ENCP_VIDEO_VSPULS_ELINE CBUS_REG_ADDR(ENCP_VIDEO_VSPULS_ELINE)
#define P_ENCP_VIDEO_EQPULS_BEGIN CBUS_REG_ADDR(ENCP_VIDEO_EQPULS_BEGIN)
#define P_ENCP_VIDEO_EQPULS_END CBUS_REG_ADDR(ENCP_VIDEO_EQPULS_END)
#define P_ENCP_VIDEO_EQPULS_BLINE CBUS_REG_ADDR(ENCP_VIDEO_EQPULS_BLINE)
#define P_ENCP_VIDEO_EQPULS_ELINE CBUS_REG_ADDR(ENCP_VIDEO_EQPULS_ELINE)
#define P_ENCP_VIDEO_HAVON_END CBUS_REG_ADDR(ENCP_VIDEO_HAVON_END)
#define P_ENCP_VIDEO_HAVON_BEGIN CBUS_REG_ADDR(ENCP_VIDEO_HAVON_BEGIN)
#define P_ENCP_VIDEO_VAVON_ELINE CBUS_REG_ADDR(ENCP_VIDEO_VAVON_ELINE)
#define P_ENCP_VIDEO_VAVON_BLINE CBUS_REG_ADDR(ENCP_VIDEO_VAVON_BLINE)
#define P_ENCP_VIDEO_HSO_BEGIN CBUS_REG_ADDR(ENCP_VIDEO_HSO_BEGIN)
#define P_ENCP_VIDEO_HSO_END CBUS_REG_ADDR(ENCP_VIDEO_HSO_END)
#define P_ENCP_VIDEO_VSO_BEGIN CBUS_REG_ADDR(ENCP_VIDEO_VSO_BEGIN)
#define P_ENCP_VIDEO_VSO_END CBUS_REG_ADDR(ENCP_VIDEO_VSO_END)
#define P_ENCP_VIDEO_VSO_BLINE CBUS_REG_ADDR(ENCP_VIDEO_VSO_BLINE)
#define P_ENCP_VIDEO_VSO_ELINE CBUS_REG_ADDR(ENCP_VIDEO_VSO_ELINE)
#define P_ENCP_VIDEO_SYNC_WAVE_CURVE CBUS_REG_ADDR(ENCP_VIDEO_SYNC_WAVE_CURVE)
#define P_ENCP_VIDEO_MAX_LNCNT CBUS_REG_ADDR(ENCP_VIDEO_MAX_LNCNT)
#define P_ENCP_VIDEO_SY_VAL CBUS_REG_ADDR(ENCP_VIDEO_SY_VAL)
#define P_ENCP_VIDEO_SY2_VAL CBUS_REG_ADDR(ENCP_VIDEO_SY2_VAL)
#define P_ENCP_VIDEO_BLANKY_VAL CBUS_REG_ADDR(ENCP_VIDEO_BLANKY_VAL)
#define P_ENCP_VIDEO_BLANKPB_VAL CBUS_REG_ADDR(ENCP_VIDEO_BLANKPB_VAL)
#define P_ENCP_VIDEO_BLANKPR_VAL CBUS_REG_ADDR(ENCP_VIDEO_BLANKPR_VAL)
#define P_ENCP_VIDEO_HOFFST CBUS_REG_ADDR(ENCP_VIDEO_HOFFST)
#define P_ENCP_VIDEO_VOFFST CBUS_REG_ADDR(ENCP_VIDEO_VOFFST)
#define P_ENCP_VIDEO_RGB_CTRL CBUS_REG_ADDR(ENCP_VIDEO_RGB_CTRL)
#define P_ENCP_VIDEO_FILT_CTRL CBUS_REG_ADDR(ENCP_VIDEO_FILT_CTRL)
#define P_ENCP_VIDEO_OFLD_VPEQ_OFST CBUS_REG_ADDR(ENCP_VIDEO_OFLD_VPEQ_OFST)
#define P_ENCP_VIDEO_OFLD_VOAV_OFST CBUS_REG_ADDR(ENCP_VIDEO_OFLD_VOAV_OFST)
#define P_ENCP_VIDEO_MATRIX_CB CBUS_REG_ADDR(ENCP_VIDEO_MATRIX_CB)
#define P_ENCP_VIDEO_MATRIX_CR CBUS_REG_ADDR(ENCP_VIDEO_MATRIX_CR)
#define P_ENCP_VIDEO_RGBIN_CTRL CBUS_REG_ADDR(ENCP_VIDEO_RGBIN_CTRL)
#define P_ENCP_MACV_BLANKY_VAL CBUS_REG_ADDR(ENCP_MACV_BLANKY_VAL)
#define P_ENCP_MACV_MAXY_VAL CBUS_REG_ADDR(ENCP_MACV_MAXY_VAL)
#define P_ENCP_MACV_1ST_PSSYNC_STRT CBUS_REG_ADDR(ENCP_MACV_1ST_PSSYNC_STRT)
#define P_ENCP_MACV_PSSYNC_STRT CBUS_REG_ADDR(ENCP_MACV_PSSYNC_STRT)
#define P_ENCP_MACV_AGC_STRT CBUS_REG_ADDR(ENCP_MACV_AGC_STRT)
#define P_ENCP_MACV_AGC_END CBUS_REG_ADDR(ENCP_MACV_AGC_END)
#define P_ENCP_MACV_WAVE_END CBUS_REG_ADDR(ENCP_MACV_WAVE_END)
#define P_ENCP_MACV_STRTLINE CBUS_REG_ADDR(ENCP_MACV_STRTLINE)
#define P_ENCP_MACV_ENDLINE CBUS_REG_ADDR(ENCP_MACV_ENDLINE)
#define P_ENCP_MACV_TS_CNT_MAX_L CBUS_REG_ADDR(ENCP_MACV_TS_CNT_MAX_L)
#define P_ENCP_MACV_TS_CNT_MAX_H CBUS_REG_ADDR(ENCP_MACV_TS_CNT_MAX_H)
#define P_ENCP_MACV_TIME_DOWN CBUS_REG_ADDR(ENCP_MACV_TIME_DOWN)
#define P_ENCP_MACV_TIME_LO CBUS_REG_ADDR(ENCP_MACV_TIME_LO)
#define P_ENCP_MACV_TIME_UP CBUS_REG_ADDR(ENCP_MACV_TIME_UP)
#define P_ENCP_MACV_TIME_RST CBUS_REG_ADDR(ENCP_MACV_TIME_RST)
#define P_ENCP_VBI_CTRL CBUS_REG_ADDR(ENCP_VBI_CTRL)
#define P_ENCP_VBI_SETTING CBUS_REG_ADDR(ENCP_VBI_SETTING)
#define P_ENCP_VBI_BEGIN CBUS_REG_ADDR(ENCP_VBI_BEGIN)
#define P_ENCP_VBI_WIDTH CBUS_REG_ADDR(ENCP_VBI_WIDTH)
#define P_ENCP_VBI_HVAL CBUS_REG_ADDR(ENCP_VBI_HVAL)
#define P_ENCP_VBI_DATA0 CBUS_REG_ADDR(ENCP_VBI_DATA0)
#define P_ENCP_VBI_DATA1 CBUS_REG_ADDR(ENCP_VBI_DATA1)
#define P_C656_HS_ST CBUS_REG_ADDR(C656_HS_ST)
#define P_C656_HS_ED CBUS_REG_ADDR(C656_HS_ED)
#define P_C656_VS_LNST_E CBUS_REG_ADDR(C656_VS_LNST_E)
#define P_C656_VS_LNST_O CBUS_REG_ADDR(C656_VS_LNST_O)
#define P_C656_VS_LNED_E CBUS_REG_ADDR(C656_VS_LNED_E)
#define P_C656_VS_LNED_O CBUS_REG_ADDR(C656_VS_LNED_O)
#define P_C656_FS_LNST CBUS_REG_ADDR(C656_FS_LNST)
#define P_C656_FS_LNED CBUS_REG_ADDR(C656_FS_LNED)
#define P_ENCI_VIDEO_MODE CBUS_REG_ADDR(ENCI_VIDEO_MODE)
#define P_ENCI_VIDEO_MODE_ADV CBUS_REG_ADDR(ENCI_VIDEO_MODE_ADV)
#define P_ENCI_VIDEO_FSC_ADJ CBUS_REG_ADDR(ENCI_VIDEO_FSC_ADJ)
#define P_ENCI_VIDEO_BRIGHT CBUS_REG_ADDR(ENCI_VIDEO_BRIGHT)
#define P_ENCI_VIDEO_CONT CBUS_REG_ADDR(ENCI_VIDEO_CONT)
#define P_ENCI_VIDEO_SAT CBUS_REG_ADDR(ENCI_VIDEO_SAT)
#define P_ENCI_VIDEO_HUE CBUS_REG_ADDR(ENCI_VIDEO_HUE)
#define P_ENCI_VIDEO_SCH CBUS_REG_ADDR(ENCI_VIDEO_SCH)
#define P_ENCI_SYNC_MODE CBUS_REG_ADDR(ENCI_SYNC_MODE)
#define P_ENCI_SYNC_CTRL CBUS_REG_ADDR(ENCI_SYNC_CTRL)
#define P_ENCI_SYNC_HSO_BEGIN CBUS_REG_ADDR(ENCI_SYNC_HSO_BEGIN)
#define P_ENCI_SYNC_HSO_END CBUS_REG_ADDR(ENCI_SYNC_HSO_END)
#define P_ENCI_SYNC_VSO_EVN CBUS_REG_ADDR(ENCI_SYNC_VSO_EVN)
#define P_ENCI_SYNC_VSO_ODD CBUS_REG_ADDR(ENCI_SYNC_VSO_ODD)
#define P_ENCI_SYNC_VSO_EVNLN CBUS_REG_ADDR(ENCI_SYNC_VSO_EVNLN)
#define P_ENCI_SYNC_VSO_ODDLN CBUS_REG_ADDR(ENCI_SYNC_VSO_ODDLN)
#define P_ENCI_SYNC_HOFFST CBUS_REG_ADDR(ENCI_SYNC_HOFFST)
#define P_ENCI_SYNC_VOFFST CBUS_REG_ADDR(ENCI_SYNC_VOFFST)
#define P_ENCI_SYNC_ADJ CBUS_REG_ADDR(ENCI_SYNC_ADJ)
#define P_ENCI_RGB_SETTING CBUS_REG_ADDR(ENCI_RGB_SETTING)
#define P_ENCI_DE_H_BEGIN CBUS_REG_ADDR(ENCI_DE_H_BEGIN)
#define P_ENCI_DE_H_END CBUS_REG_ADDR(ENCI_DE_H_END)
#define P_ENCI_DE_V_BEGIN_EVEN CBUS_REG_ADDR(ENCI_DE_V_BEGIN_EVEN)
#define P_ENCI_DE_V_END_EVEN CBUS_REG_ADDR(ENCI_DE_V_END_EVEN)
#define P_ENCI_DE_V_BEGIN_ODD CBUS_REG_ADDR(ENCI_DE_V_BEGIN_ODD)
#define P_ENCI_DE_V_END_ODD CBUS_REG_ADDR(ENCI_DE_V_END_ODD)
#define P_ENCI_VBI_SETTING CBUS_REG_ADDR(ENCI_VBI_SETTING)
#define P_ENCI_VBI_CCDT_EVN CBUS_REG_ADDR(ENCI_VBI_CCDT_EVN)
#define P_ENCI_VBI_CCDT_ODD CBUS_REG_ADDR(ENCI_VBI_CCDT_ODD)
#define P_ENCI_VBI_CC525_LN CBUS_REG_ADDR(ENCI_VBI_CC525_LN)
#define P_ENCI_VBI_CC625_LN CBUS_REG_ADDR(ENCI_VBI_CC625_LN)
#define P_ENCI_VBI_WSSDT CBUS_REG_ADDR(ENCI_VBI_WSSDT)
#define P_ENCI_VBI_WSS_LN CBUS_REG_ADDR(ENCI_VBI_WSS_LN)
#define P_ENCI_VBI_CGMSDT_L CBUS_REG_ADDR(ENCI_VBI_CGMSDT_L)
#define P_ENCI_VBI_CGMSDT_H CBUS_REG_ADDR(ENCI_VBI_CGMSDT_H)
#define P_ENCI_VBI_CGMS_LN CBUS_REG_ADDR(ENCI_VBI_CGMS_LN)
#define P_ENCI_VBI_TTX_HTIME CBUS_REG_ADDR(ENCI_VBI_TTX_HTIME)
#define P_ENCI_VBI_TTX_LN CBUS_REG_ADDR(ENCI_VBI_TTX_LN)
#define P_ENCI_VBI_TTXDT0 CBUS_REG_ADDR(ENCI_VBI_TTXDT0)
#define P_ENCI_VBI_TTXDT1 CBUS_REG_ADDR(ENCI_VBI_TTXDT1)
#define P_ENCI_VBI_TTXDT2 CBUS_REG_ADDR(ENCI_VBI_TTXDT2)
#define P_ENCI_VBI_TTXDT3 CBUS_REG_ADDR(ENCI_VBI_TTXDT3)
#define P_ENCI_MACV_N0 CBUS_REG_ADDR(ENCI_MACV_N0)
#define P_ENCI_MACV_N1 CBUS_REG_ADDR(ENCI_MACV_N1)
#define P_ENCI_MACV_N2 CBUS_REG_ADDR(ENCI_MACV_N2)
#define P_ENCI_MACV_N3 CBUS_REG_ADDR(ENCI_MACV_N3)
#define P_ENCI_MACV_N4 CBUS_REG_ADDR(ENCI_MACV_N4)
#define P_ENCI_MACV_N5 CBUS_REG_ADDR(ENCI_MACV_N5)
#define P_ENCI_MACV_N6 CBUS_REG_ADDR(ENCI_MACV_N6)
#define P_ENCI_MACV_N7 CBUS_REG_ADDR(ENCI_MACV_N7)
#define P_ENCI_MACV_N8 CBUS_REG_ADDR(ENCI_MACV_N8)
#define P_ENCI_MACV_N9 CBUS_REG_ADDR(ENCI_MACV_N9)
#define P_ENCI_MACV_N10 CBUS_REG_ADDR(ENCI_MACV_N10)
#define P_ENCI_MACV_N11 CBUS_REG_ADDR(ENCI_MACV_N11)
#define P_ENCI_MACV_N12 CBUS_REG_ADDR(ENCI_MACV_N12)
#define P_ENCI_MACV_N13 CBUS_REG_ADDR(ENCI_MACV_N13)
#define P_ENCI_MACV_N14 CBUS_REG_ADDR(ENCI_MACV_N14)
#define P_ENCI_MACV_N15 CBUS_REG_ADDR(ENCI_MACV_N15)
#define P_ENCI_MACV_N16 CBUS_REG_ADDR(ENCI_MACV_N16)
#define P_ENCI_MACV_N17 CBUS_REG_ADDR(ENCI_MACV_N17)
#define P_ENCI_MACV_N18 CBUS_REG_ADDR(ENCI_MACV_N18)
#define P_ENCI_MACV_N19 CBUS_REG_ADDR(ENCI_MACV_N19)
#define P_ENCI_MACV_N20 CBUS_REG_ADDR(ENCI_MACV_N20)
#define P_ENCI_MACV_N21 CBUS_REG_ADDR(ENCI_MACV_N21)
#define P_ENCI_MACV_N22 CBUS_REG_ADDR(ENCI_MACV_N22)
#define P_ENCI_DBG_PX_RST CBUS_REG_ADDR(ENCI_DBG_PX_RST)
#define P_ENCI_DBG_FLDLN_RST CBUS_REG_ADDR(ENCI_DBG_FLDLN_RST)
#define P_ENCI_DBG_PX_INT CBUS_REG_ADDR(ENCI_DBG_PX_INT)
#define P_ENCI_DBG_FLDLN_INT CBUS_REG_ADDR(ENCI_DBG_FLDLN_INT)
#define P_ENCI_DBG_MAXPX CBUS_REG_ADDR(ENCI_DBG_MAXPX)
#define P_ENCI_DBG_MAXLN CBUS_REG_ADDR(ENCI_DBG_MAXLN)
#define P_ENCI_MACV_MAX_AMP CBUS_REG_ADDR(ENCI_MACV_MAX_AMP)
#define P_ENCI_MACV_PULSE_LO CBUS_REG_ADDR(ENCI_MACV_PULSE_LO)
#define P_ENCI_MACV_PULSE_HI CBUS_REG_ADDR(ENCI_MACV_PULSE_HI)
#define P_ENCI_MACV_BKP_MAX CBUS_REG_ADDR(ENCI_MACV_BKP_MAX)
#define P_ENCI_CFILT_CTRL CBUS_REG_ADDR(ENCI_CFILT_CTRL)
#define P_ENCI_CFILT7 CBUS_REG_ADDR(ENCI_CFILT7)
#define P_ENCI_YC_DELAY CBUS_REG_ADDR(ENCI_YC_DELAY)
#define P_ENCI_VIDEO_EN CBUS_REG_ADDR(ENCI_VIDEO_EN)
#define P_ENCI_DVI_HSO_BEGIN CBUS_REG_ADDR(ENCI_DVI_HSO_BEGIN)
#define P_ENCI_DVI_HSO_END CBUS_REG_ADDR(ENCI_DVI_HSO_END)
#define P_ENCI_DVI_VSO_BLINE_EVN CBUS_REG_ADDR(ENCI_DVI_VSO_BLINE_EVN)
#define P_ENCI_DVI_VSO_BLINE_ODD CBUS_REG_ADDR(ENCI_DVI_VSO_BLINE_ODD)
#define P_ENCI_DVI_VSO_ELINE_EVN CBUS_REG_ADDR(ENCI_DVI_VSO_ELINE_EVN)
#define P_ENCI_DVI_VSO_ELINE_ODD CBUS_REG_ADDR(ENCI_DVI_VSO_ELINE_ODD)
#define P_ENCI_DVI_VSO_BEGIN_EVN CBUS_REG_ADDR(ENCI_DVI_VSO_BEGIN_EVN)
#define P_ENCI_DVI_VSO_BEGIN_ODD CBUS_REG_ADDR(ENCI_DVI_VSO_BEGIN_ODD)
#define P_ENCI_DVI_VSO_END_EVN CBUS_REG_ADDR(ENCI_DVI_VSO_END_EVN)
#define P_ENCI_DVI_VSO_END_ODD CBUS_REG_ADDR(ENCI_DVI_VSO_END_ODD)
#define P_ENCI_CFILT_CTRL2 CBUS_REG_ADDR(ENCI_CFILT_CTRL2)
#define P_ENCP_DVI_HSO_BEGIN CBUS_REG_ADDR(ENCP_DVI_HSO_BEGIN)
#define P_ENCP_DVI_HSO_END CBUS_REG_ADDR(ENCP_DVI_HSO_END)
#define P_ENCP_DVI_VSO_BLINE_EVN CBUS_REG_ADDR(ENCP_DVI_VSO_BLINE_EVN)
#define P_ENCP_DVI_VSO_BLINE_ODD CBUS_REG_ADDR(ENCP_DVI_VSO_BLINE_ODD)
#define P_ENCP_DVI_VSO_ELINE_EVN CBUS_REG_ADDR(ENCP_DVI_VSO_ELINE_EVN)
#define P_ENCP_DVI_VSO_ELINE_ODD CBUS_REG_ADDR(ENCP_DVI_VSO_ELINE_ODD)
#define P_ENCP_DVI_VSO_BEGIN_EVN CBUS_REG_ADDR(ENCP_DVI_VSO_BEGIN_EVN)
#define P_ENCP_DVI_VSO_BEGIN_ODD CBUS_REG_ADDR(ENCP_DVI_VSO_BEGIN_ODD)
#define P_ENCP_DVI_VSO_END_EVN CBUS_REG_ADDR(ENCP_DVI_VSO_END_EVN)
#define P_ENCP_DVI_VSO_END_ODD CBUS_REG_ADDR(ENCP_DVI_VSO_END_ODD)
#define P_ENCP_DE_H_BEGIN CBUS_REG_ADDR(ENCP_DE_H_BEGIN)
#define P_ENCP_DE_H_END CBUS_REG_ADDR(ENCP_DE_H_END)
#define P_ENCP_DE_V_BEGIN_EVEN CBUS_REG_ADDR(ENCP_DE_V_BEGIN_EVEN)
#define P_ENCP_DE_V_END_EVEN CBUS_REG_ADDR(ENCP_DE_V_END_EVEN)
#define P_ENCP_DE_V_BEGIN_ODD CBUS_REG_ADDR(ENCP_DE_V_BEGIN_ODD)
#define P_ENCP_DE_V_END_ODD CBUS_REG_ADDR(ENCP_DE_V_END_ODD)
#define P_ENCT_VIDEO_EN CBUS_REG_ADDR(ENCT_VIDEO_EN)
#define P_ENCT_VIDEO_MODE CBUS_REG_ADDR(ENCT_VIDEO_MODE)
#define P_ENCT_VIDEO_MODE_ADV CBUS_REG_ADDR(ENCT_VIDEO_MODE_ADV)
#define P_ENCT_VIDEO_MAX_PXCNT CBUS_REG_ADDR(ENCT_VIDEO_MAX_PXCNT)
#define P_ENCT_VIDEO_HAVON_END CBUS_REG_ADDR(ENCT_VIDEO_HAVON_END)
#define P_ENCT_VIDEO_HAVON_BEGIN CBUS_REG_ADDR(ENCT_VIDEO_HAVON_BEGIN)
#define P_ENCT_VIDEO_VAVON_ELINE CBUS_REG_ADDR(ENCT_VIDEO_VAVON_ELINE)
#define P_ENCT_VIDEO_VAVON_BLINE CBUS_REG_ADDR(ENCT_VIDEO_VAVON_BLINE)
#define P_ENCT_VIDEO_HSO_BEGIN CBUS_REG_ADDR(ENCT_VIDEO_HSO_BEGIN)
#define P_ENCT_VIDEO_HSO_END CBUS_REG_ADDR(ENCT_VIDEO_HSO_END)
#define P_ENCT_VIDEO_VSO_BEGIN CBUS_REG_ADDR(ENCT_VIDEO_VSO_BEGIN)
#define P_ENCT_VIDEO_VSO_END CBUS_REG_ADDR(ENCT_VIDEO_VSO_END)
#define P_ENCT_VIDEO_VSO_BLINE CBUS_REG_ADDR(ENCT_VIDEO_VSO_BLINE)
#define P_ENCT_VIDEO_VSO_ELINE CBUS_REG_ADDR(ENCT_VIDEO_VSO_ELINE)
#define P_ENCT_VIDEO_MAX_LNCNT CBUS_REG_ADDR(ENCT_VIDEO_MAX_LNCNT)
#define P_VENC_VFIFO2VD_CTL2 CBUS_REG_ADDR(VENC_VFIFO2VD_CTL2)
#define P_VENC_DVI_SETTING_MORE CBUS_REG_ADDR(VENC_DVI_SETTING_MORE)
#define P_ENCT_VIDEO_FILT_CTRL CBUS_REG_ADDR(ENCT_VIDEO_FILT_CTRL)
#define P_VENC_VDAC_DAC0_FILT_CTRL0 CBUS_REG_ADDR(VENC_VDAC_DAC0_FILT_CTRL0)
#define P_VENC_VDAC_DAC0_FILT_CTRL1 CBUS_REG_ADDR(VENC_VDAC_DAC0_FILT_CTRL1)
#define P_VENC_VDAC_DAC1_FILT_CTRL0 CBUS_REG_ADDR(VENC_VDAC_DAC1_FILT_CTRL0)
#define P_VENC_VDAC_DAC1_FILT_CTRL1 CBUS_REG_ADDR(VENC_VDAC_DAC1_FILT_CTRL1)
#define P_VENC_VDAC_DAC2_FILT_CTRL0 CBUS_REG_ADDR(VENC_VDAC_DAC2_FILT_CTRL0)
#define P_VENC_VDAC_DAC2_FILT_CTRL1 CBUS_REG_ADDR(VENC_VDAC_DAC2_FILT_CTRL1)
#define P_VENC_VDAC_DAC3_FILT_CTRL0 CBUS_REG_ADDR(VENC_VDAC_DAC3_FILT_CTRL0)
#define P_VENC_VDAC_DAC3_FILT_CTRL1 CBUS_REG_ADDR(VENC_VDAC_DAC3_FILT_CTRL1)
#define P_L_GAMMA_CNTL_PORT CBUS_REG_ADDR(L_GAMMA_CNTL_PORT)
#define P_GAMMA_CNTL_PORT CBUS_REG_ADDR(GAMMA_CNTL_PORT)
#define P_GAMMA_VCOM_POL CBUS_REG_ADDR(GAMMA_VCOM_POL)
#define P_GAMMA_RVS_OUT CBUS_REG_ADDR(GAMMA_RVS_OUT)
#define P_ADR_RDY CBUS_REG_ADDR(ADR_RDY)
#define P_WR_RDY CBUS_REG_ADDR(WR_RDY)
#define P_RD_RDY CBUS_REG_ADDR(RD_RDY)
#define P_GAMMA_TR CBUS_REG_ADDR(GAMMA_TR)
#define P_GAMMA_SET CBUS_REG_ADDR(GAMMA_SET)
#define P_GAMMA_EN CBUS_REG_ADDR(GAMMA_EN)
#define P_GAMMA_DATA_PORT CBUS_REG_ADDR(GAMMA_DATA_PORT)
#define P_GAMMA_ADDR_PORT CBUS_REG_ADDR(GAMMA_ADDR_PORT)
#define P_H_RD CBUS_REG_ADDR(H_RD)
#define P_H_AUTO_INC CBUS_REG_ADDR(H_AUTO_INC)
#define P_H_SEL_R CBUS_REG_ADDR(H_SEL_R)
#define P_H_SEL_G CBUS_REG_ADDR(H_SEL_G)
#define P_H_SEL_B CBUS_REG_ADDR(H_SEL_B)
#define P_HADR_MSB CBUS_REG_ADDR(HADR_MSB)
#define P_HADR CBUS_REG_ADDR(HADR)
#define P_GAMMA_VCOM_HSWITCH_ADDR CBUS_REG_ADDR(GAMMA_VCOM_HSWITCH_ADDR)
#define P_RGB_BASE_ADDR CBUS_REG_ADDR(RGB_BASE_ADDR)
#define P_RGB_COEFF_ADDR CBUS_REG_ADDR(RGB_COEFF_ADDR)
#define P_POL_CNTL_ADDR CBUS_REG_ADDR(POL_CNTL_ADDR)
#define P_DCLK_SEL CBUS_REG_ADDR(DCLK_SEL)
#define P_TCON_VSYNC_SEL_DVI CBUS_REG_ADDR(TCON_VSYNC_SEL_DVI)
#define P_TCON_HSYNC_SEL_DVI CBUS_REG_ADDR(TCON_HSYNC_SEL_DVI)
#define P_TCON_DE_SEL_DVI CBUS_REG_ADDR(TCON_DE_SEL_DVI)
#define P_CPH3_POL CBUS_REG_ADDR(CPH3_POL)
#define P_CPH2_POL CBUS_REG_ADDR(CPH2_POL)
#define P_CPH1_POL CBUS_REG_ADDR(CPH1_POL)
#define P_TCON_DE_SEL CBUS_REG_ADDR(TCON_DE_SEL)
#define P_TCON_VS_SEL CBUS_REG_ADDR(TCON_VS_SEL)
#define P_TCON_HS_SEL CBUS_REG_ADDR(TCON_HS_SEL)
#define P_DE_POL CBUS_REG_ADDR(DE_POL)
#define P_VS_POL CBUS_REG_ADDR(VS_POL)
#define P_HS_POL CBUS_REG_ADDR(HS_POL)
#define P_DITH_CNTL_ADDR CBUS_REG_ADDR(DITH_CNTL_ADDR)
#define P_DITH10_EN CBUS_REG_ADDR(DITH10_EN)
#define P_DITH8_EN CBUS_REG_ADDR(DITH8_EN)
#define P_DITH_MD CBUS_REG_ADDR(DITH_MD)
#define P_DITH10_CNTL_MSB CBUS_REG_ADDR(DITH10_CNTL_MSB)
#define P_DITH10_CNTL CBUS_REG_ADDR(DITH10_CNTL)
#define P_DITH8_CNTL_MSB CBUS_REG_ADDR(DITH8_CNTL_MSB)
#define P_DITH8_CNTL CBUS_REG_ADDR(DITH8_CNTL)
#define P_STH1_HS_ADDR CBUS_REG_ADDR(STH1_HS_ADDR)
#define P_STH1_HE_ADDR CBUS_REG_ADDR(STH1_HE_ADDR)
#define P_STH1_VS_ADDR CBUS_REG_ADDR(STH1_VS_ADDR)
#define P_STH1_VE_ADDR CBUS_REG_ADDR(STH1_VE_ADDR)
#define P_STH2_HS_ADDR CBUS_REG_ADDR(STH2_HS_ADDR)
#define P_STH2_HE_ADDR CBUS_REG_ADDR(STH2_HE_ADDR)
#define P_STH2_VS_ADDR CBUS_REG_ADDR(STH2_VS_ADDR)
#define P_STH2_VE_ADDR CBUS_REG_ADDR(STH2_VE_ADDR)
#define P_OEH_HS_ADDR CBUS_REG_ADDR(OEH_HS_ADDR)
#define P_OEH_HE_ADDR CBUS_REG_ADDR(OEH_HE_ADDR)
#define P_OEH_VS_ADDR CBUS_REG_ADDR(OEH_VS_ADDR)
#define P_OEH_VE_ADDR CBUS_REG_ADDR(OEH_VE_ADDR)
#define P_VCOM_HSWITCH_ADDR CBUS_REG_ADDR(VCOM_HSWITCH_ADDR)
#define P_VCOM_VS_ADDR CBUS_REG_ADDR(VCOM_VS_ADDR)
#define P_VCOM_VE_ADDR CBUS_REG_ADDR(VCOM_VE_ADDR)
#define P_CPV1_HS_ADDR CBUS_REG_ADDR(CPV1_HS_ADDR)
#define P_CPV1_HE_ADDR CBUS_REG_ADDR(CPV1_HE_ADDR)
#define P_CPV1_VS_ADDR CBUS_REG_ADDR(CPV1_VS_ADDR)
#define P_CPV1_VE_ADDR CBUS_REG_ADDR(CPV1_VE_ADDR)
#define P_CPV2_HS_ADDR CBUS_REG_ADDR(CPV2_HS_ADDR)
#define P_CPV2_HE_ADDR CBUS_REG_ADDR(CPV2_HE_ADDR)
#define P_CPV2_VS_ADDR CBUS_REG_ADDR(CPV2_VS_ADDR)
#define P_CPV2_VE_ADDR CBUS_REG_ADDR(CPV2_VE_ADDR)
#define P_STV1_HS_ADDR CBUS_REG_ADDR(STV1_HS_ADDR)
#define P_STV1_HE_ADDR CBUS_REG_ADDR(STV1_HE_ADDR)
#define P_STV1_VS_ADDR CBUS_REG_ADDR(STV1_VS_ADDR)
#define P_STV1_VE_ADDR CBUS_REG_ADDR(STV1_VE_ADDR)
#define P_STV2_HS_ADDR CBUS_REG_ADDR(STV2_HS_ADDR)
#define P_STV2_HE_ADDR CBUS_REG_ADDR(STV2_HE_ADDR)
#define P_STV2_VS_ADDR CBUS_REG_ADDR(STV2_VS_ADDR)
#define P_STV2_VE_ADDR CBUS_REG_ADDR(STV2_VE_ADDR)
#define P_OEV1_HS_ADDR CBUS_REG_ADDR(OEV1_HS_ADDR)
#define P_OEV1_HE_ADDR CBUS_REG_ADDR(OEV1_HE_ADDR)
#define P_OEV1_VS_ADDR CBUS_REG_ADDR(OEV1_VS_ADDR)
#define P_OEV1_VE_ADDR CBUS_REG_ADDR(OEV1_VE_ADDR)
#define P_OEV2_HS_ADDR CBUS_REG_ADDR(OEV2_HS_ADDR)
#define P_OEV2_HE_ADDR CBUS_REG_ADDR(OEV2_HE_ADDR)
#define P_OEV2_VS_ADDR CBUS_REG_ADDR(OEV2_VS_ADDR)
#define P_OEV2_VE_ADDR CBUS_REG_ADDR(OEV2_VE_ADDR)
#define P_OEV3_HS_ADDR CBUS_REG_ADDR(OEV3_HS_ADDR)
#define P_OEV3_HE_ADDR CBUS_REG_ADDR(OEV3_HE_ADDR)
#define P_OEV3_VS_ADDR CBUS_REG_ADDR(OEV3_VS_ADDR)
#define P_OEV3_VE_ADDR CBUS_REG_ADDR(OEV3_VE_ADDR)
#define P_LCD_PWR_ADDR CBUS_REG_ADDR(LCD_PWR_ADDR)
#define P_LCD_VDD CBUS_REG_ADDR(LCD_VDD)
#define P_LCD_VBL CBUS_REG_ADDR(LCD_VBL)
#define P_LCD_GPI_MSB CBUS_REG_ADDR(LCD_GPI_MSB)
#define P_LCD_GPIO CBUS_REG_ADDR(LCD_GPIO)
#define P_LCD_PWM0_LO_ADDR CBUS_REG_ADDR(LCD_PWM0_LO_ADDR)
#define P_LCD_PWM0_HI_ADDR CBUS_REG_ADDR(LCD_PWM0_HI_ADDR)
#define P_LCD_PWM1_LO_ADDR CBUS_REG_ADDR(LCD_PWM1_LO_ADDR)
#define P_LCD_PWM1_HI_ADDR CBUS_REG_ADDR(LCD_PWM1_HI_ADDR)
#define P_INV_CNT_ADDR CBUS_REG_ADDR(INV_CNT_ADDR)
#define P_INV_EN CBUS_REG_ADDR(INV_EN)
#define P_INV_CNT_MSB CBUS_REG_ADDR(INV_CNT_MSB)
#define P_INV_CNT CBUS_REG_ADDR(INV_CNT)
#define P_TCON_MISC_SEL_ADDR CBUS_REG_ADDR(TCON_MISC_SEL_ADDR)
#define P_STH2_SEL CBUS_REG_ADDR(STH2_SEL)
#define P_STH1_SEL CBUS_REG_ADDR(STH1_SEL)
#define P_OEH_SEL CBUS_REG_ADDR(OEH_SEL)
#define P_VCOM_SEL CBUS_REG_ADDR(VCOM_SEL)
#define P_DB_LINE_SW CBUS_REG_ADDR(DB_LINE_SW)
#define P_CPV2_SEL CBUS_REG_ADDR(CPV2_SEL)
#define P_CPV1_SEL CBUS_REG_ADDR(CPV1_SEL)
#define P_STV2_SEL CBUS_REG_ADDR(STV2_SEL)
#define P_STV1_SEL CBUS_REG_ADDR(STV1_SEL)
#define P_OEV_UNITE CBUS_REG_ADDR(OEV_UNITE)
#define P_OEV3_SEL CBUS_REG_ADDR(OEV3_SEL)
#define P_OEV2_SEL CBUS_REG_ADDR(OEV2_SEL)
#define P_OEV1_SEL CBUS_REG_ADDR(OEV1_SEL)
#define P_DUAL_PORT_CNTL_ADDR CBUS_REG_ADDR(DUAL_PORT_CNTL_ADDR)
#define P_OUTPUT_YUV CBUS_REG_ADDR(OUTPUT_YUV)
#define P_DUAL_IDF CBUS_REG_ADDR(DUAL_IDF)
#define P_DUAL_ISF CBUS_REG_ADDR(DUAL_ISF)
#define P_LCD_ANALOG_SEL_CPH3 CBUS_REG_ADDR(LCD_ANALOG_SEL_CPH3)
#define P_LCD_ANALOG_3PHI_CLK_SEL CBUS_REG_ADDR(LCD_ANALOG_3PHI_CLK_SEL)
#define P_LCD_LVDS_SEL54 CBUS_REG_ADDR(LCD_LVDS_SEL54)
#define P_LCD_LVDS_SEL27 CBUS_REG_ADDR(LCD_LVDS_SEL27)
#define P_LCD_TTL_SEL CBUS_REG_ADDR(LCD_TTL_SEL)
#define P_DUAL_LVDC_EN CBUS_REG_ADDR(DUAL_LVDC_EN)
#define P_PORT_SWP CBUS_REG_ADDR(PORT_SWP)
#define P_RGB_SWP CBUS_REG_ADDR(RGB_SWP)
#define P_BIT_SWP CBUS_REG_ADDR(BIT_SWP)
#define P_LVDS_CLK_CNTL CBUS_REG_ADDR(LVDS_CLK_CNTL)
#define P_LVDS_PHY_CNTL0 CBUS_REG_ADDR(LVDS_PHY_CNTL0)
#define P_LVDS_PHY_CNTL1 CBUS_REG_ADDR(LVDS_PHY_CNTL1)
#define P_LVDS_PHY_CNTL2 CBUS_REG_ADDR(LVDS_PHY_CNTL2)
#define P_LVDS_PHY_CNTL3 CBUS_REG_ADDR(LVDS_PHY_CNTL3)
#define P_LVDS_SRG_TEST CBUS_REG_ADDR(LVDS_SRG_TEST)
#define P_LVDS_BIST_MUX0 CBUS_REG_ADDR(LVDS_BIST_MUX0)
#define P_LVDS_BIST_MUX1 CBUS_REG_ADDR(LVDS_BIST_MUX1)
#define P_LVDS_BIST_FIXED0 CBUS_REG_ADDR(LVDS_BIST_FIXED0)
#define P_LVDS_BIST_FIXED1 CBUS_REG_ADDR(LVDS_BIST_FIXED1)
#define P_LVDS_BIST_CNTL0 CBUS_REG_ADDR(LVDS_BIST_CNTL0)
#define P_LVDS_CLKB_CLKA CBUS_REG_ADDR(LVDS_CLKB_CLKA)
#define P_LVDS_GEN_CTNL CBUS_REG_ADDR(LVDS_GEN_CTNL)
#define P_LVDS_PACK_CNTL_ADDR CBUS_REG_ADDR(LVDS_PACK_CNTL_ADDR)
#define P_LVDS_USE_TCON CBUS_REG_ADDR(LVDS_USE_TCON)
#define P_LVDS_DUAL CBUS_REG_ADDR(LVDS_DUAL)
#define P_PN_SWP CBUS_REG_ADDR(PN_SWP)
#define P_LSB_FIRST CBUS_REG_ADDR(LSB_FIRST)
#define P_LVDS_RESV CBUS_REG_ADDR(LVDS_RESV)
#define P_ODD_EVEN_SWP CBUS_REG_ADDR(ODD_EVEN_SWP)
#define P_LVDS_REPACK CBUS_REG_ADDR(LVDS_REPACK)
#define P_DE_HS_ADDR CBUS_REG_ADDR(DE_HS_ADDR)
#define P_DE_HE_ADDR CBUS_REG_ADDR(DE_HE_ADDR)
#define P_DE_VS_ADDR CBUS_REG_ADDR(DE_VS_ADDR)
#define P_DE_VE_ADDR CBUS_REG_ADDR(DE_VE_ADDR)
#define P_HSYNC_HS_ADDR CBUS_REG_ADDR(HSYNC_HS_ADDR)
#define P_HSYNC_HE_ADDR CBUS_REG_ADDR(HSYNC_HE_ADDR)
#define P_HSYNC_VS_ADDR CBUS_REG_ADDR(HSYNC_VS_ADDR)
#define P_HSYNC_VE_ADDR CBUS_REG_ADDR(HSYNC_VE_ADDR)
#define P_VSYNC_HS_ADDR CBUS_REG_ADDR(VSYNC_HS_ADDR)
#define P_VSYNC_HE_ADDR CBUS_REG_ADDR(VSYNC_HE_ADDR)
#define P_VSYNC_VS_ADDR CBUS_REG_ADDR(VSYNC_VS_ADDR)
#define P_VSYNC_VE_ADDR CBUS_REG_ADDR(VSYNC_VE_ADDR)
#define P_LCD_MCU_CTL CBUS_REG_ADDR(LCD_MCU_CTL)
#define P_LCD_MCU_DATA_0 CBUS_REG_ADDR(LCD_MCU_DATA_0)
#define P_LCD_MCU_DATA_1 CBUS_REG_ADDR(LCD_MCU_DATA_1)
#define P_VPU_OSD1_MMC_CTRL CBUS_REG_ADDR(VPU_OSD1_MMC_CTRL)
#define P_VPU_OSD2_MMC_CTRL CBUS_REG_ADDR(VPU_OSD2_MMC_CTRL)
#define P_VPU_VD1_MMC_CTRL CBUS_REG_ADDR(VPU_VD1_MMC_CTRL)
#define P_VPU_VD2_MMC_CTRL CBUS_REG_ADDR(VPU_VD2_MMC_CTRL)
#define P_VPU_DI_IF1_MMC_CTRL CBUS_REG_ADDR(VPU_DI_IF1_MMC_CTRL)
#define P_VPU_DI_MEM_MMC_CTRL CBUS_REG_ADDR(VPU_DI_MEM_MMC_CTRL)
#define P_VPU_DI_INP_MMC_CTRL CBUS_REG_ADDR(VPU_DI_INP_MMC_CTRL)
#define P_VPU_DI_MTNRD_MMC_CTRL CBUS_REG_ADDR(VPU_DI_MTNRD_MMC_CTRL)
#define P_VPU_DI_CHAN2_MMC_CTRL CBUS_REG_ADDR(VPU_DI_CHAN2_MMC_CTRL)
#define P_VPU_DI_MTNWR_MMC_CTRL CBUS_REG_ADDR(VPU_DI_MTNWR_MMC_CTRL)
#define P_VPU_DI_NRWR_MMC_CTRL CBUS_REG_ADDR(VPU_DI_NRWR_MMC_CTRL)
#define P_VPU_DI_DIWR_MMC_CTRL CBUS_REG_ADDR(VPU_DI_DIWR_MMC_CTRL)
#define P_VPU_VDIN_MMC_CTRL CBUS_REG_ADDR(VPU_VDIN_MMC_CTRL)
#define P_VPU_DVIN_MMC_CTRL CBUS_REG_ADDR(VPU_DVIN_MMC_CTRL)
#define P_VPU_BT656_MMC_CTRL CBUS_REG_ADDR(VPU_BT656_MMC_CTRL)
#define P_VPU_VIU_VENC_MUX_CTRL CBUS_REG_ADDR(VPU_VIU_VENC_MUX_CTRL)
#define P_VLD_STATUS_CTRL CBUS_REG_ADDR(VLD_STATUS_CTRL)
#define P_MPEG1_2_REG CBUS_REG_ADDR(MPEG1_2_REG)
#define P_F_CODE_REG CBUS_REG_ADDR(F_CODE_REG)
#define P_PIC_HEAD_INFO CBUS_REG_ADDR(PIC_HEAD_INFO)
#define P_SLICE_VER_POS_PIC_TYPE CBUS_REG_ADDR(SLICE_VER_POS_PIC_TYPE)
#define P_QP_VALUE_REG CBUS_REG_ADDR(QP_VALUE_REG)
#define P_MBA_INC CBUS_REG_ADDR(MBA_INC)
#define P_MB_MOTION_MODE CBUS_REG_ADDR(MB_MOTION_MODE)
#define P_POWER_CTL_VLD CBUS_REG_ADDR(POWER_CTL_VLD)
#define P_MB_WIDTH CBUS_REG_ADDR(MB_WIDTH)
#define P_SLICE_QP CBUS_REG_ADDR(SLICE_QP)
#define P_PRE_START_CODE CBUS_REG_ADDR(PRE_START_CODE)
#define P_SLICE_START_BYTE_01 CBUS_REG_ADDR(SLICE_START_BYTE_01)
#define P_SLICE_START_BYTE_23 CBUS_REG_ADDR(SLICE_START_BYTE_23)
#define P_RESYNC_MARKER_LENGTH CBUS_REG_ADDR(RESYNC_MARKER_LENGTH)
#define P_FST_FOR_MV_X CBUS_REG_ADDR(FST_FOR_MV_X)
#define P_FST_FOR_MV_Y CBUS_REG_ADDR(FST_FOR_MV_Y)
#define P_SCD_FOR_MV_X CBUS_REG_ADDR(SCD_FOR_MV_X)
#define P_SCD_FOR_MV_Y CBUS_REG_ADDR(SCD_FOR_MV_Y)
#define P_FST_BAK_MV_X CBUS_REG_ADDR(FST_BAK_MV_X)
#define P_FST_BAK_MV_Y CBUS_REG_ADDR(FST_BAK_MV_Y)
#define P_SCD_BAK_MV_X CBUS_REG_ADDR(SCD_BAK_MV_X)
#define P_SCD_BAK_MV_Y CBUS_REG_ADDR(SCD_BAK_MV_Y)
#define P_HALF_PEL_ONE CBUS_REG_ADDR(HALF_PEL_ONE)
#define P_HALF_PEL_TWO CBUS_REG_ADDR(HALF_PEL_TWO)
#define P_VIFF_BIT_CNT CBUS_REG_ADDR(VIFF_BIT_CNT)
#define P_BYTE_ALIGN_PEAK_HI CBUS_REG_ADDR(BYTE_ALIGN_PEAK_HI)
#define P_BYTE_ALIGN_PEAK_LO CBUS_REG_ADDR(BYTE_ALIGN_PEAK_LO)
#define P_NEXT_ALIGN_PEAK CBUS_REG_ADDR(NEXT_ALIGN_PEAK)
#define P_VC1_CONTROL_REG CBUS_REG_ADDR(VC1_CONTROL_REG)
#define P_PMV1_X CBUS_REG_ADDR(PMV1_X)
#define P_PMV1_Y CBUS_REG_ADDR(PMV1_Y)
#define P_PMV2_X CBUS_REG_ADDR(PMV2_X)
#define P_PMV2_Y CBUS_REG_ADDR(PMV2_Y)
#define P_PMV3_X CBUS_REG_ADDR(PMV3_X)
#define P_PMV3_Y CBUS_REG_ADDR(PMV3_Y)
#define P_PMV4_X CBUS_REG_ADDR(PMV4_X)
#define P_PMV4_Y CBUS_REG_ADDR(PMV4_Y)
#define P_M4_TABLE_SELECT CBUS_REG_ADDR(M4_TABLE_SELECT)
#define P_M4_CONTROL_REG CBUS_REG_ADDR(M4_CONTROL_REG)
#define P_BLOCK_NUM CBUS_REG_ADDR(BLOCK_NUM)
#define P_PATTERN_CODE CBUS_REG_ADDR(PATTERN_CODE)
#define P_MB_INFO CBUS_REG_ADDR(MB_INFO)
#define P_VLD_DC_PRED CBUS_REG_ADDR(VLD_DC_PRED)
#define P_VLD_ERROR_MASK CBUS_REG_ADDR(VLD_ERROR_MASK)
#define P_VLD_DC_PRED_C CBUS_REG_ADDR(VLD_DC_PRED_C)
#define P_LAST_SLICE_MV_ADDR CBUS_REG_ADDR(LAST_SLICE_MV_ADDR)
#define P_LAST_MVX CBUS_REG_ADDR(LAST_MVX)
#define P_LAST_MVY CBUS_REG_ADDR(LAST_MVY)
#define P_VLD_C38 CBUS_REG_ADDR(VLD_C38)
#define P_VLD_C39 CBUS_REG_ADDR(VLD_C39)
#define P_VLD_STATUS CBUS_REG_ADDR(VLD_STATUS)
#define P_VLD_SHIFT_STATUS CBUS_REG_ADDR(VLD_SHIFT_STATUS)
#define P_VOFF_STATUS CBUS_REG_ADDR(VOFF_STATUS)
#define P_VLD_C3D CBUS_REG_ADDR(VLD_C3D)
#define P_VLD_DBG_INDEX CBUS_REG_ADDR(VLD_DBG_INDEX)
#define P_VLD_DBG_DATA CBUS_REG_ADDR(VLD_DBG_DATA)
#define P_VLD_MEM_VIFIFO_START_PTR CBUS_REG_ADDR(VLD_MEM_VIFIFO_START_PTR)
#define P_VLD_MEM_VIFIFO_CURR_PTR CBUS_REG_ADDR(VLD_MEM_VIFIFO_CURR_PTR)
#define P_VLD_MEM_VIFIFO_END_PTR CBUS_REG_ADDR(VLD_MEM_VIFIFO_END_PTR)
#define P_VLD_MEM_VIFIFO_BYTES_AVAIL CBUS_REG_ADDR(VLD_MEM_VIFIFO_BYTES_AVAIL)
#define P_VLD_MEM_VIFIFO_CONTROL CBUS_REG_ADDR(VLD_MEM_VIFIFO_CONTROL)
#define P_VLD_MEM_VIFIFO_WP CBUS_REG_ADDR(VLD_MEM_VIFIFO_WP)
#define P_VLD_MEM_VIFIFO_RP CBUS_REG_ADDR(VLD_MEM_VIFIFO_RP)
#define P_VLD_MEM_VIFIFO_LEVEL CBUS_REG_ADDR(VLD_MEM_VIFIFO_LEVEL)
#define P_VLD_MEM_VIFIFO_BUF_CNTL CBUS_REG_ADDR(VLD_MEM_VIFIFO_BUF_CNTL)
#define P_VLD_TIME_STAMP_CNTL CBUS_REG_ADDR(VLD_TIME_STAMP_CNTL)
#define P_VLD_TIME_STAMP_SYNC_0 CBUS_REG_ADDR(VLD_TIME_STAMP_SYNC_0)
#define P_VLD_TIME_STAMP_SYNC_1 CBUS_REG_ADDR(VLD_TIME_STAMP_SYNC_1)
#define P_VLD_TIME_STAMP_0 CBUS_REG_ADDR(VLD_TIME_STAMP_0)
#define P_VLD_TIME_STAMP_1 CBUS_REG_ADDR(VLD_TIME_STAMP_1)
#define P_VLD_TIME_STAMP_2 CBUS_REG_ADDR(VLD_TIME_STAMP_2)
#define P_VLD_TIME_STAMP_3 CBUS_REG_ADDR(VLD_TIME_STAMP_3)
#define P_VLD_TIME_STAMP_LENGTH CBUS_REG_ADDR(VLD_TIME_STAMP_LENGTH)
#define P_VLD_MEM_VIFIFO_WRAP_COUNT CBUS_REG_ADDR(VLD_MEM_VIFIFO_WRAP_COUNT)
#define P_VLD_MEM_VIFIFO_MEM_CTL CBUS_REG_ADDR(VLD_MEM_VIFIFO_MEM_CTL)
#define P_VCOP_CTRL_REG CBUS_REG_ADDR(VCOP_CTRL_REG)
#define P_QP_CTRL_REG CBUS_REG_ADDR(QP_CTRL_REG)
#define P_INTRA_QUANT_MATRIX CBUS_REG_ADDR(INTRA_QUANT_MATRIX)
#define P_NON_I_QUANT_MATRIX CBUS_REG_ADDR(NON_I_QUANT_MATRIX)
#define P_DC_SCALER CBUS_REG_ADDR(DC_SCALER)
#define P_DC_AC_CTRL CBUS_REG_ADDR(DC_AC_CTRL)
#define P_DC_AC_SCALE_MUL CBUS_REG_ADDR(DC_AC_SCALE_MUL)
#define P_DC_AC_SCALE_DIV CBUS_REG_ADDR(DC_AC_SCALE_DIV)
#define P_POWER_CTL_IQIDCT CBUS_REG_ADDR(POWER_CTL_IQIDCT)
#define P_RV_AI_Y_X CBUS_REG_ADDR(RV_AI_Y_X)
#define P_RV_AI_U_X CBUS_REG_ADDR(RV_AI_U_X)
#define P_RV_AI_V_X CBUS_REG_ADDR(RV_AI_V_X)
#define P_RV_AI_MB_COUNT CBUS_REG_ADDR(RV_AI_MB_COUNT)
#define P_NEXT_INTRA_DMA_ADDRESS CBUS_REG_ADDR(NEXT_INTRA_DMA_ADDRESS)
#define P_IQIDCT_CONTROL CBUS_REG_ADDR(IQIDCT_CONTROL)
#define P_IQIDCT_DEBUG_INFO_0 CBUS_REG_ADDR(IQIDCT_DEBUG_INFO_0)
#define P_DEBLK_CMD CBUS_REG_ADDR(DEBLK_CMD)
#define P_IQIDCT_DEBUG_IDCT CBUS_REG_ADDR(IQIDCT_DEBUG_IDCT)
#define P_DCAC_DMA_CTRL CBUS_REG_ADDR(DCAC_DMA_CTRL)
#define P_DCAC_DMA_ADDRESS CBUS_REG_ADDR(DCAC_DMA_ADDRESS)
#define P_DCAC_CPU_ADDRESS CBUS_REG_ADDR(DCAC_CPU_ADDRESS)
#define P_DCAC_CPU_DATA CBUS_REG_ADDR(DCAC_CPU_DATA)
#define P_DCAC_MB_COUNT CBUS_REG_ADDR(DCAC_MB_COUNT)
#define P_IQ_QUANT CBUS_REG_ADDR(IQ_QUANT)
#define P_VC1_BITPLANE_CTL CBUS_REG_ADDR(VC1_BITPLANE_CTL)
#define P_RAM_TEST_CMD CBUS_REG_ADDR(RAM_TEST_CMD)
#define P_RAM_TEST_ADDR CBUS_REG_ADDR(RAM_TEST_ADDR)
#define P_RAM_TEST_DATAH CBUS_REG_ADDR(RAM_TEST_DATAH)
#define P_RAM_TEST_DATAL CBUS_REG_ADDR(RAM_TEST_DATAL)
#define P_RAM_TEST_RD_CMD CBUS_REG_ADDR(RAM_TEST_RD_CMD)
#define P_RAM_TEST_WR_CMD CBUS_REG_ADDR(RAM_TEST_WR_CMD)
#define P_IDCT_TM2_PT0 CBUS_REG_ADDR(IDCT_TM2_PT0)
#define P_IDCT_TM2_PT1 CBUS_REG_ADDR(IDCT_TM2_PT1)
#define P_IDCT_TM1_PT0 CBUS_REG_ADDR(IDCT_TM1_PT0)
#define P_IDCT_TM1_PT1 CBUS_REG_ADDR(IDCT_TM1_PT1)
#define P_IQ_OMEM_PT0 CBUS_REG_ADDR(IQ_OMEM_PT0)
#define P_IQ_OMEM_PT1 CBUS_REG_ADDR(IQ_OMEM_PT1)
#define P_MC_IMEM_PT0 CBUS_REG_ADDR(MC_IMEM_PT0)
#define P_ALL_RAM_PTS CBUS_REG_ADDR(ALL_RAM_PTS)
#define P_QM_WEN CBUS_REG_ADDR(QM_WEN)
#define P_IQIDCT_ENABLE CBUS_REG_ADDR(IQIDCT_ENABLE)
#define P_INTRA_QM CBUS_REG_ADDR(INTRA_QM)
#define P_NINTRA_QM CBUS_REG_ADDR(NINTRA_QM)
#define P_INTRA_MODE CBUS_REG_ADDR(INTRA_MODE)
#define P_AUDIO_COP_CTL2 CBUS_REG_ADDR(AUDIO_COP_CTL2)
#define P_OPERAND_M_CTL CBUS_REG_ADDR(OPERAND_M_CTL)
#define P_OPERAND1_ADDR CBUS_REG_ADDR(OPERAND1_ADDR)
#define P_OPERAND2_ADDR CBUS_REG_ADDR(OPERAND2_ADDR)
#define P_RESULT_M_CTL CBUS_REG_ADDR(RESULT_M_CTL)
#define P_RESULT1_ADDR CBUS_REG_ADDR(RESULT1_ADDR)
#define P_RESULT2_ADDR CBUS_REG_ADDR(RESULT2_ADDR)
#define P_ADD_SHFT_CTL CBUS_REG_ADDR(ADD_SHFT_CTL)
#define P_OPERAND_ONE_H CBUS_REG_ADDR(OPERAND_ONE_H)
#define P_OPERAND_ONE_L CBUS_REG_ADDR(OPERAND_ONE_L)
#define P_OPERAND_TWO_H CBUS_REG_ADDR(OPERAND_TWO_H)
#define P_OPERAND_TWO_L CBUS_REG_ADDR(OPERAND_TWO_L)
#define P_RESULT_H CBUS_REG_ADDR(RESULT_H)
#define P_RESULT_M CBUS_REG_ADDR(RESULT_M)
#define P_RESULT_L CBUS_REG_ADDR(RESULT_L)
#define P_WMEM_R_PTR CBUS_REG_ADDR(WMEM_R_PTR)
#define P_WMEM_W_PTR CBUS_REG_ADDR(WMEM_W_PTR)
#define P_AUDIO_LAYER CBUS_REG_ADDR(AUDIO_LAYER)
#define P_AC3_DECODING CBUS_REG_ADDR(AC3_DECODING)
#define P_AC3_DYNAMIC CBUS_REG_ADDR(AC3_DYNAMIC)
#define P_AC3_MELODY CBUS_REG_ADDR(AC3_MELODY)
#define P_AC3_VOCAL CBUS_REG_ADDR(AC3_VOCAL)
#define P_ASSIST_AMR1_INT0 CBUS_REG_ADDR(ASSIST_AMR1_INT0)
#define P_ASSIST_AMR1_INT1 CBUS_REG_ADDR(ASSIST_AMR1_INT1)
#define P_ASSIST_AMR1_INT2 CBUS_REG_ADDR(ASSIST_AMR1_INT2)
#define P_ASSIST_AMR1_INT3 CBUS_REG_ADDR(ASSIST_AMR1_INT3)
#define P_ASSIST_AMR1_INT4 CBUS_REG_ADDR(ASSIST_AMR1_INT4)
#define P_ASSIST_AMR1_INT5 CBUS_REG_ADDR(ASSIST_AMR1_INT5)
#define P_ASSIST_AMR1_INT6 CBUS_REG_ADDR(ASSIST_AMR1_INT6)
#define P_ASSIST_AMR1_INT7 CBUS_REG_ADDR(ASSIST_AMR1_INT7)
#define P_ASSIST_AMR1_INT8 CBUS_REG_ADDR(ASSIST_AMR1_INT8)
#define P_ASSIST_AMR1_INT9 CBUS_REG_ADDR(ASSIST_AMR1_INT9)
#define P_ASSIST_AMR1_INTA CBUS_REG_ADDR(ASSIST_AMR1_INTA)
#define P_ASSIST_AMR1_INTB CBUS_REG_ADDR(ASSIST_AMR1_INTB)
#define P_ASSIST_AMR1_INTC CBUS_REG_ADDR(ASSIST_AMR1_INTC)
#define P_ASSIST_AMR1_INTD CBUS_REG_ADDR(ASSIST_AMR1_INTD)
#define P_ASSIST_AMR1_INTE CBUS_REG_ADDR(ASSIST_AMR1_INTE)
#define P_ASSIST_AMR1_INTF CBUS_REG_ADDR(ASSIST_AMR1_INTF)
#define P_ASSIST_AMR2_INT0 CBUS_REG_ADDR(ASSIST_AMR2_INT0)
#define P_ASSIST_AMR2_INT1 CBUS_REG_ADDR(ASSIST_AMR2_INT1)
#define P_ASSIST_AMR2_INT2 CBUS_REG_ADDR(ASSIST_AMR2_INT2)
#define P_ASSIST_AMR2_INT3 CBUS_REG_ADDR(ASSIST_AMR2_INT3)
#define P_ASSIST_AMR2_INT4 CBUS_REG_ADDR(ASSIST_AMR2_INT4)
#define P_ASSIST_AMR2_INT5 CBUS_REG_ADDR(ASSIST_AMR2_INT5)
#define P_ASSIST_AMR2_INT6 CBUS_REG_ADDR(ASSIST_AMR2_INT6)
#define P_ASSIST_AMR2_INT7 CBUS_REG_ADDR(ASSIST_AMR2_INT7)
#define P_ASSIST_AMR2_INT8 CBUS_REG_ADDR(ASSIST_AMR2_INT8)
#define P_ASSIST_AMR2_INT9 CBUS_REG_ADDR(ASSIST_AMR2_INT9)
#define P_ASSIST_AMR2_INTA CBUS_REG_ADDR(ASSIST_AMR2_INTA)
#define P_ASSIST_AMR2_INTB CBUS_REG_ADDR(ASSIST_AMR2_INTB)
#define P_ASSIST_AMR2_INTC CBUS_REG_ADDR(ASSIST_AMR2_INTC)
#define P_ASSIST_AMR2_INTD CBUS_REG_ADDR(ASSIST_AMR2_INTD)
#define P_ASSIST_AMR2_INTE CBUS_REG_ADDR(ASSIST_AMR2_INTE)
#define P_ASSIST_AMR2_INTF CBUS_REG_ADDR(ASSIST_AMR2_INTF)
#define P_ASSIST_AMR_MBOX1_INT CBUS_REG_ADDR(ASSIST_AMR_MBOX1_INT)
#define P_ASSIST_AMR_MBOX2_INT CBUS_REG_ADDR(ASSIST_AMR_MBOX2_INT)
#define P_ASSIST_AMR_SCRATCH0 CBUS_REG_ADDR(ASSIST_AMR_SCRATCH0)
#define P_ASSIST_AMR_SCRATCH1 CBUS_REG_ADDR(ASSIST_AMR_SCRATCH1)
#define P_ASSIST_AMR_SCRATCH2 CBUS_REG_ADDR(ASSIST_AMR_SCRATCH2)
#define P_ASSIST_AMR_SCRATCH3 CBUS_REG_ADDR(ASSIST_AMR_SCRATCH3)
#define P_ASSIST_HW_REV CBUS_REG_ADDR(ASSIST_HW_REV)
#define P_ASSIST_CBUS_ARB CBUS_REG_ADDR(ASSIST_CBUS_ARB)
#define P_ASSIST_POR_CONFIG CBUS_REG_ADDR(ASSIST_POR_CONFIG)
#define P_ASSIST_SPARE16_REG1 CBUS_REG_ADDR(ASSIST_SPARE16_REG1)
#define P_ASSIST_SPARE16_REG2 CBUS_REG_ADDR(ASSIST_SPARE16_REG2)
#define P_ASSIST_SPARE8_REG1 CBUS_REG_ADDR(ASSIST_SPARE8_REG1)
#define P_ASSIST_SPARE8_REG2 CBUS_REG_ADDR(ASSIST_SPARE8_REG2)
#define P_ASSIST_SPARE8_REG3 CBUS_REG_ADDR(ASSIST_SPARE8_REG3)
#define P_AC3_CTRL_REG1 CBUS_REG_ADDR(AC3_CTRL_REG1)
#define P_AC3_CTRL_REG2 CBUS_REG_ADDR(AC3_CTRL_REG2)
#define P_AC3_CTRL_REG3 CBUS_REG_ADDR(AC3_CTRL_REG3)
#define P_AC3_CTRL_REG4 CBUS_REG_ADDR(AC3_CTRL_REG4)
#define P_ASSIST_PMEM_SPLIT CBUS_REG_ADDR(ASSIST_PMEM_SPLIT)
#define P_TIMER0_LO CBUS_REG_ADDR(TIMER0_LO)
#define P_TIMER0_HI CBUS_REG_ADDR(TIMER0_HI)
#define P_TIMER1_LO CBUS_REG_ADDR(TIMER1_LO)
#define P_TIMER1_HI CBUS_REG_ADDR(TIMER1_HI)
#define P_DMA_INT CBUS_REG_ADDR(DMA_INT)
#define P_DMA_INT_MSK CBUS_REG_ADDR(DMA_INT_MSK)
#define P_DMA_INT2 CBUS_REG_ADDR(DMA_INT2)
#define P_DMA_INT_MSK2 CBUS_REG_ADDR(DMA_INT_MSK2)
#define P_ASSIST_MBOX0_IRQ_REG CBUS_REG_ADDR(ASSIST_MBOX0_IRQ_REG)
#define P_ASSIST_MBOX0_CLR_REG CBUS_REG_ADDR(ASSIST_MBOX0_CLR_REG)
#define P_ASSIST_MBOX0_MASK CBUS_REG_ADDR(ASSIST_MBOX0_MASK)
#define P_ASSIST_MBOX0_FIQ_SEL CBUS_REG_ADDR(ASSIST_MBOX0_FIQ_SEL)
#define P_ASSIST_MBOX1_IRQ_REG CBUS_REG_ADDR(ASSIST_MBOX1_IRQ_REG)
#define P_ASSIST_MBOX1_CLR_REG CBUS_REG_ADDR(ASSIST_MBOX1_CLR_REG)
#define P_ASSIST_MBOX1_MASK CBUS_REG_ADDR(ASSIST_MBOX1_MASK)
#define P_ASSIST_MBOX1_FIQ_SEL CBUS_REG_ADDR(ASSIST_MBOX1_FIQ_SEL)
#define P_ASSIST_MBOX2_IRQ_REG CBUS_REG_ADDR(ASSIST_MBOX2_IRQ_REG)
#define P_ASSIST_MBOX2_CLR_REG CBUS_REG_ADDR(ASSIST_MBOX2_CLR_REG)
#define P_ASSIST_MBOX2_MASK CBUS_REG_ADDR(ASSIST_MBOX2_MASK)
#define P_ASSIST_MBOX2_FIQ_SEL CBUS_REG_ADDR(ASSIST_MBOX2_FIQ_SEL)
/**
APB Bus registers
**/
#define P_PCTL_SCFG_ADDR APB_REG_ADDR(PCTL_SCFG_ADDR)
#define P_PCTL_SCTL_ADDR APB_REG_ADDR(PCTL_SCTL_ADDR)
#define P_PCTL_STAT_ADDR APB_REG_ADDR(PCTL_STAT_ADDR)
#define P_PCTL_MCMD_ADDR APB_REG_ADDR(PCTL_MCMD_ADDR)
#define P_PCTL_POWCTL_ADDR APB_REG_ADDR(PCTL_POWCTL_ADDR)
#define P_PCTL_POWSTAT_ADDR APB_REG_ADDR(PCTL_POWSTAT_ADDR)
#define P_PCTL_MCFG_ADDR APB_REG_ADDR(PCTL_MCFG_ADDR)
#define P_PCTL_PPCFG_ADDR APB_REG_ADDR(PCTL_PPCFG_ADDR)
#define P_PCTL_MSTAT_ADDR APB_REG_ADDR(PCTL_MSTAT_ADDR)
#define P_PCTL_ODTCFG_ADDR APB_REG_ADDR(PCTL_ODTCFG_ADDR)
#define P_PCTL_DQSECFG_ADDR APB_REG_ADDR(PCTL_DQSECFG_ADDR)
#define P_PCTL_DTUPDES_ADDR APB_REG_ADDR(PCTL_DTUPDES_ADDR)
#define P_PCTL_DTUNA_ADDR APB_REG_ADDR(PCTL_DTUNA_ADDR)
#define P_PCTL_DTUNE_ADDR APB_REG_ADDR(PCTL_DTUNE_ADDR)
#define P_PCTL_DTUPRD0_ADDR APB_REG_ADDR(PCTL_DTUPRD0_ADDR)
#define P_PCTL_DTUPRD1_ADDR APB_REG_ADDR(PCTL_DTUPRD1_ADDR)
#define P_PCTL_DTUPRD2_ADDR APB_REG_ADDR(PCTL_DTUPRD2_ADDR)
#define P_PCTL_DTUPRD3_ADDR APB_REG_ADDR(PCTL_DTUPRD3_ADDR)
#define P_PCTL_DTUAWDT_ADDR APB_REG_ADDR(PCTL_DTUAWDT_ADDR)
#define P_PCTL_TOGCNT1U_ADDR APB_REG_ADDR(PCTL_TOGCNT1U_ADDR)
#define P_PCTL_TINIT_ADDR APB_REG_ADDR(PCTL_TINIT_ADDR)
#define P_PCTL_TRSTH_ADDR APB_REG_ADDR(PCTL_TRSTH_ADDR)
#define P_PCTL_TOGCNT100N_ADDR APB_REG_ADDR(PCTL_TOGCNT100N_ADDR)
#define P_PCTL_TREFI_ADDR APB_REG_ADDR(PCTL_TREFI_ADDR)
#define P_PCTL_TMRD_ADDR APB_REG_ADDR(PCTL_TMRD_ADDR)
#define P_PCTL_TRFC_ADDR APB_REG_ADDR(PCTL_TRFC_ADDR)
#define P_PCTL_TRP_ADDR APB_REG_ADDR(PCTL_TRP_ADDR)
#define P_PCTL_TRTW_ADDR APB_REG_ADDR(PCTL_TRTW_ADDR)
#define P_PCTL_TAL_ADDR APB_REG_ADDR(PCTL_TAL_ADDR)
#define P_PCTL_TCL_ADDR APB_REG_ADDR(PCTL_TCL_ADDR)
#define P_PCTL_TCWL_ADDR APB_REG_ADDR(PCTL_TCWL_ADDR)
#define P_PCTL_TRAS_ADDR APB_REG_ADDR(PCTL_TRAS_ADDR)
#define P_PCTL_TRC_ADDR APB_REG_ADDR(PCTL_TRC_ADDR)
#define P_PCTL_TRCD_ADDR APB_REG_ADDR(PCTL_TRCD_ADDR)
#define P_PCTL_TRRD_ADDR APB_REG_ADDR(PCTL_TRRD_ADDR)
#define P_PCTL_TRTP_ADDR APB_REG_ADDR(PCTL_TRTP_ADDR)
#define P_PCTL_TWR_ADDR APB_REG_ADDR(PCTL_TWR_ADDR)
#define P_PCTL_TWTR_ADDR APB_REG_ADDR(PCTL_TWTR_ADDR)
#define P_PCTL_TEXSR_ADDR APB_REG_ADDR(PCTL_TEXSR_ADDR)
#define P_PCTL_TXP_ADDR APB_REG_ADDR(PCTL_TXP_ADDR)
#define P_PCTL_TXPDLL_ADDR APB_REG_ADDR(PCTL_TXPDLL_ADDR)
#define P_PCTL_TZQCS_ADDR APB_REG_ADDR(PCTL_TZQCS_ADDR)
#define P_PCTL_TZQCSI_ADDR APB_REG_ADDR(PCTL_TZQCSI_ADDR)
#define P_PCTL_TDQS_ADDR APB_REG_ADDR(PCTL_TDQS_ADDR)
#define P_PCTL_TCKSRE_ADDR APB_REG_ADDR(PCTL_TCKSRE_ADDR)
#define P_PCTL_TCKSRX_ADDR APB_REG_ADDR(PCTL_TCKSRX_ADDR)
#define P_PCTL_TCKE_ADDR APB_REG_ADDR(PCTL_TCKE_ADDR)
#define P_PCTL_TMOD_ADDR APB_REG_ADDR(PCTL_TMOD_ADDR)
#define P_PCTL_TRSTL_ADDR APB_REG_ADDR(PCTL_TRSTL_ADDR)
#define P_PCTL_TZQCL_ADDR APB_REG_ADDR(PCTL_TZQCL_ADDR)
#define P_PCTL_DWLCFG0_ADDR APB_REG_ADDR(PCTL_DWLCFG0_ADDR)
#define P_PCTL_DWLCFG1_ADDR APB_REG_ADDR(PCTL_DWLCFG1_ADDR)
#define P_PCTL_DWLCFG2_ADDR APB_REG_ADDR(PCTL_DWLCFG2_ADDR)
#define P_PCTL_DWLCFG3_ADDR APB_REG_ADDR(PCTL_DWLCFG3_ADDR)
#define P_PCTL_ECCCFG_ADDR APB_REG_ADDR(PCTL_ECCCFG_ADDR)
#define P_PCTL_ECCTST_ADDR APB_REG_ADDR(PCTL_ECCTST_ADDR)
#define P_PCTL_ECCCLR_ADDR APB_REG_ADDR(PCTL_ECCCLR_ADDR)
#define P_PCTL_ECCLOG_ADDR APB_REG_ADDR(PCTL_ECCLOG_ADDR)
#define P_PCTL_ADDRMAP_ADDR APB_REG_ADDR(PCTL_ADDRMAP_ADDR)
#define P_PCTL_IDDEC0_ADDR APB_REG_ADDR(PCTL_IDDEC0_ADDR)
#define P_PCTL_IDDEC1_ADDR APB_REG_ADDR(PCTL_IDDEC1_ADDR)
#define P_PCTL_DTUWACTL_ADDR APB_REG_ADDR(PCTL_DTUWACTL_ADDR)
#define P_PCTL_DTURACTL_ADDR APB_REG_ADDR(PCTL_DTURACTL_ADDR)
#define P_PCTL_DTUCFG_ADDR APB_REG_ADDR(PCTL_DTUCFG_ADDR)
#define P_PCTL_DTUECTL_ADDR APB_REG_ADDR(PCTL_DTUECTL_ADDR)
#define P_PCTL_DTUWD0_ADDR APB_REG_ADDR(PCTL_DTUWD0_ADDR)
#define P_PCTL_DTUWD1_ADDR APB_REG_ADDR(PCTL_DTUWD1_ADDR)
#define P_PCTL_DTUWD2_ADDR APB_REG_ADDR(PCTL_DTUWD2_ADDR)
#define P_PCTL_DTUWD3_ADDR APB_REG_ADDR(PCTL_DTUWD3_ADDR)
#define P_PCTL_DTUWDM_ADDR APB_REG_ADDR(PCTL_DTUWDM_ADDR)
#define P_PCTL_DTURD0_ADDR APB_REG_ADDR(PCTL_DTURD0_ADDR)
#define P_PCTL_DTURD1_ADDR APB_REG_ADDR(PCTL_DTURD1_ADDR)
#define P_PCTL_DTURD2_ADDR APB_REG_ADDR(PCTL_DTURD2_ADDR)
#define P_PCTL_DTURD3_ADDR APB_REG_ADDR(PCTL_DTURD3_ADDR)
#define P_PCTL_DTULFSRWD_ADDR APB_REG_ADDR(PCTL_DTULFSRWD_ADDR)
#define P_PCTL_DTULFSRRD_ADDR APB_REG_ADDR(PCTL_DTULFSRRD_ADDR)
#define P_PCTL_DTUEAF_ADDR APB_REG_ADDR(PCTL_DTUEAF_ADDR)
#define P_PCTL_PHYCR_ADDR APB_REG_ADDR(PCTL_PHYCR_ADDR)
#define P_PCTL_PHYSR_ADDR APB_REG_ADDR(PCTL_PHYSR_ADDR)
#define P_PCTL_IOCR_ADDR APB_REG_ADDR(PCTL_IOCR_ADDR)
#define P_PCTL_RSLR0_ADDR APB_REG_ADDR(PCTL_RSLR0_ADDR)
#define P_PCTL_RSLR1_ADDR APB_REG_ADDR(PCTL_RSLR1_ADDR)
#define P_PCTL_RSLR2_ADDR APB_REG_ADDR(PCTL_RSLR2_ADDR)
#define P_PCTL_RSLR3_ADDR APB_REG_ADDR(PCTL_RSLR3_ADDR)
#define P_PCTL_RDGR0_ADDR APB_REG_ADDR(PCTL_RDGR0_ADDR)
#define P_PCTL_RDGR1_ADDR APB_REG_ADDR(PCTL_RDGR1_ADDR)
#define P_PCTL_RDGR2_ADDR APB_REG_ADDR(PCTL_RDGR2_ADDR)
#define P_PCTL_RDGR3_ADDR APB_REG_ADDR(PCTL_RDGR3_ADDR)
#define P_PCTL_ZQCR_ADDR APB_REG_ADDR(PCTL_ZQCR_ADDR)
#define P_PCTL_ZQSR_ADDR APB_REG_ADDR(PCTL_ZQSR_ADDR)
#define P_PCTL_DLLCR_ADDR APB_REG_ADDR(PCTL_DLLCR_ADDR)
#define P_PCTL_DLLCR0_ADDR APB_REG_ADDR(PCTL_DLLCR0_ADDR)
#define P_PCTL_DLLCR1_ADDR APB_REG_ADDR(PCTL_DLLCR1_ADDR)
#define P_PCTL_DLLCR2_ADDR APB_REG_ADDR(PCTL_DLLCR2_ADDR)
#define P_PCTL_DLLCR3_ADDR APB_REG_ADDR(PCTL_DLLCR3_ADDR)
#define P_PCTL_DLLCR4_ADDR APB_REG_ADDR(PCTL_DLLCR4_ADDR)
#define P_PCTL_DLLCR5_ADDR APB_REG_ADDR(PCTL_DLLCR5_ADDR)
#define P_PCTL_DLLCR6_ADDR APB_REG_ADDR(PCTL_DLLCR6_ADDR)
#define P_PCTL_DLLCR7_ADDR APB_REG_ADDR(PCTL_DLLCR7_ADDR)
#define P_PCTL_DLLCR8_ADDR APB_REG_ADDR(PCTL_DLLCR8_ADDR)
#define P_PCTL_DLLCR9_ADDR APB_REG_ADDR(PCTL_DLLCR9_ADDR)
#define P_PCTL_DQTR0_ADDR APB_REG_ADDR(PCTL_DQTR0_ADDR)
#define P_PCTL_DQTR1_ADDR APB_REG_ADDR(PCTL_DQTR1_ADDR)
#define P_PCTL_DQTR2_ADDR APB_REG_ADDR(PCTL_DQTR2_ADDR)
#define P_PCTL_DQTR3_ADDR APB_REG_ADDR(PCTL_DQTR3_ADDR)
#define P_PCTL_DQTR4_ADDR APB_REG_ADDR(PCTL_DQTR4_ADDR)
#define P_PCTL_DQTR5_ADDR APB_REG_ADDR(PCTL_DQTR5_ADDR)
#define P_PCTL_DQTR6_ADDR APB_REG_ADDR(PCTL_DQTR6_ADDR)
#define P_PCTL_DQTR7_ADDR APB_REG_ADDR(PCTL_DQTR7_ADDR)
#define P_PCTL_DQTR8_ADDR APB_REG_ADDR(PCTL_DQTR8_ADDR)
#define P_PCTL_DQSTR_ADDR APB_REG_ADDR(PCTL_DQSTR_ADDR)
#define P_PCTL_DQSNTR_ADDR APB_REG_ADDR(PCTL_DQSNTR_ADDR)
#define P_PCTL_PHYPVTCFG_ADDR APB_REG_ADDR(PCTL_PHYPVTCFG_ADDR)
#define P_PCTL_PHYPVTSTAT_ADDR APB_REG_ADDR(PCTL_PHYPVTSTAT_ADDR)
#define P_PCTL_PHYTUPDON_ADDR APB_REG_ADDR(PCTL_PHYTUPDON_ADDR)
#define P_PCTL_PHYTUPDDLY_ADDR APB_REG_ADDR(PCTL_PHYTUPDDLY_ADDR)
#define P_PCTL_PVTTUPDON_ADDR APB_REG_ADDR(PCTL_PVTTUPDON_ADDR)
#define P_PCTL_PVTTUPDDLY_ADDR APB_REG_ADDR(PCTL_PVTTUPDDLY_ADDR)
#define P_PCTL_PHYPVTUPDI_ADDR APB_REG_ADDR(PCTL_PHYPVTUPDI_ADDR)
#define P_PCTL_SCHCFG_ADDR APB_REG_ADDR(PCTL_SCHCFG_ADDR)
#define P_PCTL_IPVR_ADDR APB_REG_ADDR(PCTL_IPVR_ADDR)
#define P_PCTL_IPTR_ADDR APB_REG_ADDR(PCTL_IPTR_ADDR)
#define P_MMC_DDR_CTRL APB_REG_ADDR(MMC_DDR_CTRL)
#define P_MMC_REQ_CTRL APB_REG_ADDR(MMC_REQ_CTRL)
#define P_MMC_ARB_CTRL APB_REG_ADDR(MMC_ARB_CTRL)
#define P_MMC_ARB_CTRL1 APB_REG_ADDR(MMC_ARB_CTRL1)
#define P_MMC_QOS0_CTRL APB_REG_ADDR(MMC_QOS0_CTRL)
#define P_MMC_QOS0_MAX APB_REG_ADDR(MMC_QOS0_MAX)
#define P_MMC_QOS0_MIN APB_REG_ADDR(MMC_QOS0_MIN)
#define P_MMC_QOS0_LIMIT APB_REG_ADDR(MMC_QOS0_LIMIT)
#define P_MMC_QOS0_STOP APB_REG_ADDR(MMC_QOS0_STOP)
#define P_MMC_QOS1_CTRL APB_REG_ADDR(MMC_QOS1_CTRL)
#define P_MMC_QOS1_MAX APB_REG_ADDR(MMC_QOS1_MAX)
#define P_MMC_QOS1_MIN APB_REG_ADDR(MMC_QOS1_MIN)
#define P_MMC_QOS1_STOP APB_REG_ADDR(MMC_QOS1_STOP)
#define P_MMC_QOS1_LIMIT APB_REG_ADDR(MMC_QOS1_LIMIT)
#define P_MMC_QOS2_CTRL APB_REG_ADDR(MMC_QOS2_CTRL)
#define P_MMC_QOS2_MAX APB_REG_ADDR(MMC_QOS2_MAX)
#define P_MMC_QOS2_MIN APB_REG_ADDR(MMC_QOS2_MIN)
#define P_MMC_QOS2_STOP APB_REG_ADDR(MMC_QOS2_STOP)
#define P_MMC_QOS2_LIMIT APB_REG_ADDR(MMC_QOS2_LIMIT)
#define P_MMC_QOS3_CTRL APB_REG_ADDR(MMC_QOS3_CTRL)
#define P_MMC_QOS3_MAX APB_REG_ADDR(MMC_QOS3_MAX)
#define P_MMC_QOS3_MIN APB_REG_ADDR(MMC_QOS3_MIN)
#define P_MMC_QOS3_STOP APB_REG_ADDR(MMC_QOS3_STOP)
#define P_MMC_QOS3_LIMIT APB_REG_ADDR(MMC_QOS3_LIMIT)
#define P_MMC_QOS4_CTRL APB_REG_ADDR(MMC_QOS4_CTRL)
#define P_MMC_QOS4_MAX APB_REG_ADDR(MMC_QOS4_MAX)
#define P_MMC_QOS4_MIN APB_REG_ADDR(MMC_QOS4_MIN)
#define P_MMC_QOS4_STOP APB_REG_ADDR(MMC_QOS4_STOP)
#define P_MMC_QOS4_LIMIT APB_REG_ADDR(MMC_QOS4_LIMIT)
#define P_MMC_QOS5_CTRL APB_REG_ADDR(MMC_QOS5_CTRL)
#define P_MMC_QOS5_MAX APB_REG_ADDR(MMC_QOS5_MAX)
#define P_MMC_QOS5_MIN APB_REG_ADDR(MMC_QOS5_MIN)
#define P_MMC_QOS5_STOP APB_REG_ADDR(MMC_QOS5_STOP)
#define P_MMC_QOS5_LIMIT APB_REG_ADDR(MMC_QOS5_LIMIT)
#define P_MMC_QOS6_CTRL APB_REG_ADDR(MMC_QOS6_CTRL)
#define P_MMC_QOS6_MAX APB_REG_ADDR(MMC_QOS6_MAX)
#define P_MMC_QOS6_MIN APB_REG_ADDR(MMC_QOS6_MIN)
#define P_MMC_QOS6_STOP APB_REG_ADDR(MMC_QOS6_STOP)
#define P_MMC_QOS6_LIMIT APB_REG_ADDR(MMC_QOS6_LIMIT)
#define P_MMC_QOS7_CTRL APB_REG_ADDR(MMC_QOS7_CTRL)
#define P_MMC_QOS7_MAX APB_REG_ADDR(MMC_QOS7_MAX)
#define P_MMC_QOS7_MIN APB_REG_ADDR(MMC_QOS7_MIN)
#define P_MMC_QOS7_STOP APB_REG_ADDR(MMC_QOS7_STOP)
#define P_MMC_QOS7_LIMIT APB_REG_ADDR(MMC_QOS7_LIMIT)
#define P_MMC_QOSMON_CTRL APB_REG_ADDR(MMC_QOSMON_CTRL)
#define P_MMC_QOSMON_TIM APB_REG_ADDR(MMC_QOSMON_TIM)
#define P_MMC_QOSMON_MST APB_REG_ADDR(MMC_QOSMON_MST)
#define P_MMC_MON_CLKCNT APB_REG_ADDR(MMC_MON_CLKCNT)
#define P_MMC_ALL_REQCNT APB_REG_ADDR(MMC_ALL_REQCNT)
#define P_MMC_ALL_GANTCNT APB_REG_ADDR(MMC_ALL_GANTCNT)
#define P_MMC_ONE_REQCNT APB_REG_ADDR(MMC_ONE_REQCNT)
#define P_MMC_ONE_CYCLE_CNT APB_REG_ADDR(MMC_ONE_CYCLE_CNT)
#define P_MMC_ONE_DATA_CNT APB_REG_ADDR(MMC_ONE_DATA_CNT)
#define P_DC_CAV_CTRL APB_REG_ADDR(DC_CAV_CTRL)
#define P_DC_CAV_LVL3_GRANT APB_REG_ADDR(DC_CAV_LVL3_GRANT)
#define P_DC_CAV_LVL3_GH APB_REG_ADDR(DC_CAV_LVL3_GH)
#define P_DC_CAV_LVL3_FLIP APB_REG_ADDR(DC_CAV_LVL3_FLIP)
#define P_DC_CAV_LVL3_FH APB_REG_ADDR(DC_CAV_LVL3_FH)
#define P_DC_CAV_LVL3_CTRL0 APB_REG_ADDR(DC_CAV_LVL3_CTRL0)
#define P_DC_CAV_LVL3_CTRL1 APB_REG_ADDR(DC_CAV_LVL3_CTRL1)
#define P_DC_CAV_LVL3_CTRL2 APB_REG_ADDR(DC_CAV_LVL3_CTRL2)
#define P_DC_CAV_LVL3_CTRL3 APB_REG_ADDR(DC_CAV_LVL3_CTRL3)
#define P_DC_CAV_LUT_DATAL APB_REG_ADDR(DC_CAV_LUT_DATAL)
#define P_DC_CAV_LUT_DATAH APB_REG_ADDR(DC_CAV_LUT_DATAH)
#define P_DC_CAV_LUT_ADDR APB_REG_ADDR(DC_CAV_LUT_ADDR)
#define P_DC_CAV_LVL3_MODE APB_REG_ADDR(DC_CAV_LVL3_MODE)
#define P_MMC_PROT_ADDR APB_REG_ADDR(MMC_PROT_ADDR)
#define P_MMC_PROT_SELH APB_REG_ADDR(MMC_PROT_SELH)
#define P_MMC_PROT_SELL APB_REG_ADDR(MMC_PROT_SELL)
#define P_MMC_PROT_CTL_STS APB_REG_ADDR(MMC_PROT_CTL_STS)
#define P_MMC_INT_STS APB_REG_ADDR(MMC_INT_STS)
#define P_MMC_PHY_CTRL APB_REG_ADDR(MMC_PHY_CTRL)
#define P_MMC_APB3_CTRL APB_REG_ADDR(MMC_APB3_CTRL)
#define P_MMC_REQ0_CTRL APB_REG_ADDR(MMC_REQ0_CTRL)
#define P_MMC_REQ1_CTRL APB_REG_ADDR(MMC_REQ1_CTRL)
#define P_MMC_REQ2_CTRL APB_REG_ADDR(MMC_REQ2_CTRL)
#define P_MMC_REQ3_CTRL APB_REG_ADDR(MMC_REQ3_CTRL)
#define P_MMC_REQ4_CTRL APB_REG_ADDR(MMC_REQ4_CTRL)
#define P_MMC_REQ5_CTRL APB_REG_ADDR(MMC_REQ5_CTRL)
#define P_MMC_REQ6_CTRL APB_REG_ADDR(MMC_REQ6_CTRL)
#define P_MMC_REQ7_CTRL APB_REG_ADDR(MMC_REQ7_CTRL)

#endif